PC97338 datasheet(161/221 Pages) NSC

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Cleared when the CPU reads all the data in the

Holding Register or in the RX_FIFO.

UART, Sharp-IR, SIR, CEIR Modes

OE – Overrun Error.

This bit is set to 1 as soon as an overrun condition

is detected by the receiver.

Cleared upon read.

FIFOs Disabled: An overrun occurs when a new

character is completely received into the receiver

front-end section and the CPU has not yet read

the previous character in the receiver holding reg-

ister. The new character is discarded, and the re-

ceiver holding register is not affected.

FIFOs Enabled: An overrun occurs when a new

character is completely received into the receiver

front-end section and the RX_FIFO is full.

The new

character

discarded,

and

the

RX_FIFO is not affected.

MIR, FIR Modes

OE – Overrun Error.

An overrun occurs when a new character is com-

pletely received into the receiver front-end sec-

tion and the RX_FIFO or the ST_FIFO is full.

The new

character

discarded,

and

the

RX_FIFO is not affected.

Cleared upon read.

UART, Sharp-IR, SIR Modes

PE – Parity Error.

This bit is set to 1 if the received character did not

have the correct parity, as selected by the parity

control bits in the LCR register.

If the FIFOs are enabled, the Parity Error condi-

tion will be associated with the particular charac-

ter in the RX_FIFO it applies to.

In which case, the PE bit is set when the charac-

ter reaches the bottom of the RX_FIFO.

Cleared upon read.

MIR, FIR Modes

BAD_CRC – CRC Error.

Set to 1 when a mismatch between the received

CRC and the receiver-generated CRC is detect-

ed, and the last byte of the received frame has

reached the bottom of the RX_FIFO.

Cleared upon read.

UART, Sharp-IR, SIR Modes

FE – Framing Error.

This bit indicates that the received character did

not have a valid stop bit.

It is set to 1 when the stop bit is detected as a log-

ic 0.

If the FIFOs are enabled, the Framing Error con-

dition will be associated with the particular char-

acter in the RX_FIFO it applies to.

In which case, the FE bit is set when the charac-

ter reaches the bottom of the RX_FIFO.

After a Framing Error is detected, the receiver will

try to resynchronize.

If the bit following the stop bit position is 0, the re-

ceiver assumes it to be a valid start bit and the

next character is shifted in.

If that bit is 1, the receiver will enter the idle state

looking for the next start bit.

Cleared upon read.

MIR Mode

PHY_ERR – Physical Layer Error.

Set to 1 when an abort condition is detected dur-

ing the reception of a frame, and the last byte of

the frame has reached the bottom of the

RX_FIFO.

Cleared upon read.

FIR Mode

PHY_ERR – Physical Layer Error.

Set to 1 when an encoding error or the sequence

BOF-data-BOF is detected (missing EOF) during

the reception of a frame, and the last byte of the

frame has reached the bottom of the RX_FIFO.

Cleared upon read.

UART, Sharp-IR, SIR Modes

BRK – Break Event Detected.

Set to 1 when a sequence of logic 0 bits, equal or

longer than a full character transmission, is re-

ceived.

If the FIFOs are enabled, the Break condition will

be associated with the particular character in the

RX_FIFO it applies to.

In which case, the BRK bit is set when the char-

acter reaches the bottom of the RX_FIFO. When

a Break occurs only one zero character is trans-

ferred to the receiver holding register or to the

RX_FIFO.

The next character transfer takes place after at

least one logic 1 bit is received followed by a valid

start bit. Cleared upon read.

MIR, FIR Modes

MAX_LEN – Maximum Length.

Set to 1 when a frame exceeding the maximum

length has been received, and the last byte of the

frame has reached the bottom of the RX_FIFO.

Cleared upon read.

B5 TXRDY – Transmitter Ready.

This bit is set to 1 when the Transmitter Holding

It is cleared when a data character is written to

the TXD port.

B6 TXEMP – Transmitter Empty.

Set to 1 when the Transmitter is empty. The

transmitter empty condition occurs when the

Holding Register or the TX_FIFO is empty, and

the transmitter front-end is idle.

UART, Sharp-IR, SIR Modes

ER_INF – Error in RX_FIFO.

Set to 1 when at least one character with a PE,

FE or BRK condition is in the RX_FIFO.

This bit is always 0 in 16450 mode.

MIR, FIR Modes

FR_END – Frame End.

Set to 1 when the last byte (Frame End Byte) of a

received frame reaches the bottom of the

RX_FIFO.

Cleared upon read.

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