PC97338 datasheet(157/221 Pages) NSC

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FCR – FIFO Control Register Write Only

Used to enable the FIFOs, clear the FIFOs and set

the interrupt threshold levels.

Upon reset, all bits are set to 0.

FIGURE 88. FIFO Control Register

TABLE 76. TX_FIFO Level Selection

TABLE 77. RX_FIFO Level Selection

5.14.4 LCR/BSR – Link Control/Bank

Select Register

These registers share the same address.

The Link Control Register (LCR) is used to select the

communications format for data transfers in UART,

Sharp-IR and SIR modes.

The Bank select register (BSR) is used to select the

When the CPU performs a read cycle from this ad-

dress location, the BSR content is returned. The con-

tent of LCR is returned when the CPU reads the

SH_LCR register in bank 3.

During CPU write cycles, the setting of bit 7 (BKSE,

bank select enable) determines the register to be ac-

cessed.

If bit 7 is 0, both LCR and BSR are written into. If bit 7

is 1, only BSR is written into, and LCR is not affected.

This prevents the communications format from being

spuriously affected when a bank other than bank 0 is

accessed. Upon reset, all bits are set to 0.

LCR – Link Control Register

The Format of LCR is shown in Figure 88.

FIFO_EN – Enable FIFOs.

When set to 1, both TX_FIFO and RX_FIFO

are enabled.

In MIR, FIR and CEIR modes, the FIFOs are

always enabled, and the setting of this bit is ig-

nored.

RXSR – Receiver Soft Reset.

Writing a 1 to this bit position generates a re-

ceiver soft reset, whereby the receiver logic as

well as the RX_FIFO are both cleared.

This bit is automatically cleared by the hard-

ware.

TXSR – Transmitter Soft Reset.

Writing a 1 to this bit position generates a

transmitter soft reset, whereby the transmitter

logic as well as the TX_FIFO are both cleared.

This bit is automatically cleared by the hard-

ware.

Reserved.

Write 0.

B5–4 TXFTH [1–0] – TX_FIFO Interrupt Thresh-

old.

In non-extended mode, these bits have no ef-

fect, regardless of the values written into them.

In extended mode, these bits select the

TX_FIFO interrupt threshold level.

An interrupt is generated when the TX_FIFO

level drops below the threshold.

321

Reset

Required

TXSR

TXFTH0

TXFTH1

RXFTH0

RXFTH1

FIFO_EN

RXSR

Reserved

TXFTH (Bits 5-4)

TX_FIF0 Tresh.

(16 Levels)

TX_FIF0

Tresh.

(32 Levels)

00(Default)

B7–6 RXFTH [1–0] – RX_FIFO Interrupt Thresh-

old.

These bits select the RX_FIFO interrupt

threshold level.

An interrupt is generated when the RX_FIFO

level is equal to or above the threshold.

RXFTH

(Bits 7-6)

RX_FIF0

Tresh.

(16 Levels)

RX_FIF0 Tresh.

(32 Levels)

00(Default)

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