PC97338 datasheet(162/221 Pages) NSC

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5.14.7 MSR – Modem Status Register

The function of this register depends on the selected

operational mode. When UART Mode is selected, this

change information of the status lines from the MO-

DEM or Data Set. When any one of the Infrared

Modes is selected, the register function is controlled

by the setting of the IRMSSL bit in the IRCR2 register.

If IRMSSL is 0, the MSR register works the same as

in UART mode. If IRMSSL is 1, the MSR register re-

turns the value 30h, regardless of the state of the MO-

DEM input lines.

In Loopback mode, the MSR register works similarly

except that its status inputs are internally driven by

appropriate bits in the MCR register since the MO-

DEM input lines are internally disconnected. Refer to

the sections describing the MCR and EXCR1 register

for more information.

A description of the various bits of MSR, with Loop-

back disabled and UART Mode selected, is provided

below. When any of the bits 0 to 3 is set to 1, a Mo-

dem Status Interrupt is generated. Bits 0 to 3 are set

to 0 when any of the following events occurs.

1. Hardware reset.

2. The MSR register is read.

3. The operational mode is changed and the

IRMSSL bit is 0.

Note: The modem status lines have no effect on

transmitter and receiver operation. They can be used

as general purpose inputs.

FIGURE 88. Modem Status Register

5.14.8 SPR/ASCR – Scratchpad/Auxiliary

Status and Control Register

These registers share the same address.

SPR–Scratchpad Register.

This register is accessed when the module is in non-

extended mode.

It does not control the module in any way, and is in-

tended to be used by the programmer to hold data

temporarily.

ASCR–Auxiliary Status and Control Register.

This register is accessed when the extended mode of

operation is selected.

All the ASCR bits are cleared when a hardware reset

occurs or when the operational mode changes.

Bits 2 and 6 are cleared when the transmitter is soft

reset.

Bits 0, 1, 4 and 5 are cleared when the receiver is soft

reset.

The format of ASCR is shown in Figure 88.

FIGURE 88. Auxillary Status and Control

B0 DCTS – Delta Clear to Send.

Set to 1 when the CTS input changes state.

Cleared upon read.

B1 DDSR – Delta Data Set Ready.

Set to 1 when the DSR input changes state.

Cleared upon read.

B2 TERI – Ring Indicator Trailing Edge.

Set to 1 when the RI input changes from a low

state to a high state.

654

321

Reset

Required

TERI

CTS

DSR

DCD

DCTS

DDSR

DDCD

Cleared upon read.

B3 DDCD – Delta Data Carrier Detect.

Set to 1 when the DCD input changes state.

Cleared upon read.

B4 CTS – Clear to Send.

This bit returns the complement of the CTS input.

B5 DSR – Data Set Ready.

This bit returns the complement of the DSR input.

B6 RI – Ring Indicator.

This bit returns the complement of the RI input.

B7 DCD – Data Carrier Detect.

This bit returns the complement of the DCD input.

B0 RXF_TOUT – RX_FIFO Time-out.

This bit is read-only, and is set to 1 when an

RX_FIFO Time-out occurs.

321

Reset

Required

RXBSY / RXACT

TXUR

PLD/CTE

S_EOT

LOST_FR / RXWDG

RXF_TOUT

FEND_INF

TXHFE

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