PC97338 datasheet(160/221 Pages) NSC

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TABLE 81. The Module Operation Modes

5.14.6 LSR – Link Status Register

This register provides status information to the CPU

concerning the data transfer.

Bits 1 through 4 (and 7 when in MIR or FIR mode) in-

dicate link status events.

These bits are sticky, and accumulate any conditions

occurred since the last time the register was read.

These bits are cleared when any of the following

events occurs:

1. Hardware reset.

2. The receiver is soft reset.

3. The LSR register is read.

Note: This register is intended for read operations

only. Writing to this register is not recommended as it

may cause indeterminate results.

FIGURE 88. Link Status Register

DTR – Data Terminal Ready.

This bit controls the DTR signal output.

When it is set to 1, DTR is driven low.

In loopback mode this bit internally drives both

DSR and RI.

RTS – Request to Send.

This bit controls the RTS signal output.

When it is set to 1, RTS is driven low.

In loopback mode this bit internally drives both

CTS and DCD.

DMA_EN – DMA Mode Enable.

When set to 1, DMA mode of operation is en-

abled.

When data transfers are performed by a DMA

controller, the transmit and/or receive data in-

terrupts should be disabled to avoid spurious

interrupts.

Note that DMA cycles always access the data

holding registers or FIFOs, regardless of the

selected bank.

TX_DFR – Transmit Deferral.

When set to 1, transmit deferral is enabled.

Effective only when the TX_FIFO is enabled.

IR_PLS – Send Interaction Pulse.

This bit is effective only in MIR and FIR Modes.

It is set to 1 by writing 1 into it.

Writing 0 into it has no effect.

When set to 1, a 2

µs infrared interaction pulse

is transmitted at the end of the frame and the

bit is automatically cleared by the hardware.

This bit is also cleared when the transmitter is

soft reset.

The interaction pulse must be emitted at least

once every 500 ms, as long as the high-speed

connection lasts, in order to quiet slower

(115.2 kbps or below) systems that might oth-

erwise interfere with the link.

B7–5 MDSL [2–0] – Mode Select.

These bits are used to select the operational

mode as shown in Table 81.

When the mode is changed, the transmitter

and receiver are soft reset, and the modem

status events are cleared.

MDSL2

(Bit 7)

MDSL1

(Bit 6)

MDSL0

(Bit 5)

Operational Mode

000

UART (Default)

001

Reserved

Sharp-IR

011

SIR

100

MIR

101

FIR

110

CEIR

111

Reserved

B0 RXDA – Receiver Data Available.

Set to 1 when the Receiver Holding Register is

full.

If the FIFOs are enabled, this bit is set when at

least one character is in the RX_FIFO.

543

Reset

Required

PE / BAD_CRC

BRK / MAX_LEN

TXRDY

TXEMP

ER_INF / FR_END

RXDA

FE / PHY_ERR

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