PC97338 datasheet(164/221 Pages) NSC

164 / 221 page

164

www.national.com

5.15.1 LBGD – Legacy Baud Generator

Divisor Port

This port provides an alternate data path to the baud

generator divisor register. It is implemented for com-

patibility with the 16550 and to support existing legacy

software packages. New software should use the

BGD port in bank 2 to access the baud generator de-

visor register. Like the BGD port, LBGD is 16 bits wide

and is split into two 8-bit parts, LBGD(L) and LB-

GD(H), occupying consecutive address locations. A

CPU read or write access of the divisor register,

through either LBGD(L) or LBGD(H), will affect the

module operational mode as follows.

If the module is in extended mode, the module is

switched back to 16550 compatibility mode.

In addition to the EXT_SL bit, the following bits are

also cleared.

1. Bits 2 to 7 of extended-mode MCR.

2. Bit 5 and 7 of EXCR1.

3. Bits 0 to 5 of EXCR2.

4. Bits 2 and 3 of IRCR1.

If the module is in non-extended mode and the LOCK

bit is 0, the following bits will be cleared.

1. Bits 5 and 7 of EXCR1.

2. Bits 0 to 5 of EXCR2.

If the module is in non-extended mode and the LOCK

bit is 1, the content of the divisor register will not be

affected and no other action is taken.

5.15.2 LCR/BSR – Link Control/Bank

Select Registers

These registers are the same as in bank 0.

5.16 BANK 2

TABLE 83. Bank 2 Register Set

5.16.1 BGD – Baud Generator Divisor

Port

This port provides the data path to the baud generator

divisor register that holds the reload value for the

baud generator counter. Divisor values from 1 to 2

–1 can be used. See Table 84. The zero value is re-

served and must not be used. The programmed value

must be such that the baud generator output clock fre-

quency is sixteen times the desired baud rate value.

The baud generator divisor register is 16 bits wide

and is split into two independently accessible 8-bit

parts. Correspondingly, the BGD port is also 16 bits

wide and is split into two 8-bit parts, occupying con-

secutive address locations. BGD(L) is located at the

lower address and accesses the least significant part

of the baud generator divisor register, whereas

BGD(H) is located at the higher address and access-

es the most significant part. The baud generator divi-

sor register must be loaded during initialization to

ensure proper operation of the baud generator. Upon

loading either part of it, the baud generator counter is

immediately loaded.

After reset, the content of the baud generator divisor

Address

Offset

Name

Description

00h

BGD(L)

Baud Generator Divisor Port

(Low byte)

01h

BGD(H)

Baud Generator Divisor Port

(High byte)

02h

EXCR1

Extended Control Register 1

03h

LCR/BSR

Link Control/

Bank Select Register

04h

EXCR2

Extended Control Register 2

05h

Reserved

06h

TXFLV

TX_FIFO Level

07h

RXFLV

RX_FIFO Level

PC97338 датащи(PDF) 164 Page - National Semiconductor (TI)

PC97338 датащи(HTML) 164 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL