PC87351 datasheet(20/86 Pages) NSC

20 / 86 page

1.0 Signal/Pin Connection and Description (Continued)

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1.4.5

Host Interface

1.4.6

Infrared (IR)

Signal

Pin/s

I/O

Buffer Type

Description

A15-A0

11-16,

19-28

IINT

Address. These address lines of the ISA bus determine which internal

AEN

INT

Address Enable. This input disables function selection via A15-A0 when it

is high. Access during DMA transfer is NOT affected by this pin.

D7-D0

I/O

INT/O15/24

Data. Bi-directional data lines of the ISA bus. D7 is the MSB and D0 is the

LSB.

DACK1-3

50, 52,

IINT

DMA Acknowledge 1, 2 and 3. These active low signals acknowledge a

request for DMA services and enable the IORD and the IOWR input

signals during DMA transfer.

DRQ1-3

47-49

O15/24

DMA Request 1, 2, and 3. These active high output signals inform the

DMA controller that a data transfer is needed.

IOCHRDY

OD24

I/O Channel Ready. This is the I/O channel ready open drain output

signal. When IOCHRDY is driven low, the EPP extends the host cycle.

IORD

INTS

I/O Read. An active low RD input signal indicates that the microprocessor

has read data.

IOWR

INTS

I/O Write. WR is an active low input signal that indicates a write operation

from the microprocessor to the controller.

IRQ1,3-7, 9,

11-12

34,35,

37-43

I/O

INT/

OD24, O15/24

Interrupt Request 1, 3-7, 9, 11-12. IRQ polarity and output type selection

is software conﬁgurable by the logical device mapped to the IRQ line.

INTS

Master Reset. An active high MR input signal resets the device with its

default settings.

PCICLK

INPCI

PCI Clock. Up to 33 MHz.

SERIRQ

I/O

INT/O15/24

Serial IRQ. Encoded interrupts on a serial line.

INT

DMA Terminal Count. The DMA controller issues TC to indicate the

termination of a DMA transfer. TC is accepted only when a DACK signal is

active.

TC is active high in PC-AT mode, and active low in PS/2 mode.

Signal

Pin/s

I/O

Buffer Type

Description

IRRX1

INT

IR Reception 1. Primary input to receive serial data from the IR

transceiver module.

IRRX2/

IRSL0

41, 128 I/O

INT/O6/12

IRRX2 - IR Reception 2. Auxiliary IR receiver input to support two

transceiver modules.

IRSL0 - IR Control Signals 0. Output to control the IR analog front end.

IRTX

O6/12

IR Transmit. IR serial output data.

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