PC87351 datasheet(36/86 Pages) NSC

36 / 86 page

2.0 Device Architecture and Configuration (Continued)

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2.5.2

TRI-STATE Control of Parallel Port Pins

Normally, the pins of most of the SuperI/O functions can be put in TRI-STATE when the function is disabled. If the TRI-

STATE control bit of a logical device (normally bit 0 of the Configuration Register at index F0) is set to 1, and its Activate bit

(bit 0 of Activate Register at index 30) is cleared to 0, the output pins of that device are floating. The same is true for the

Parallel Port pins, but TRI-STATE control depends on the current functionality of the pins.

When the PPM is disabled or when a parallel device is connected to the port, then the TRI-STATE of the Parallel Port pins

is controlled by the Parallel Port Activate bit and TRI-STATE control bit. However, when the PPM is enabled and the external

FDD is connected (PNF=0), TRI-STATE is controlled by the corresponding FDC configuration bits.

Table 2-9 shows the standard 25-pin, D-type connector definition for Parallel Port operations in PPM mode.

1. The PNF signal is the inverse of pin 24 of the connector (PNF).

Table 2-9. Parallel Port Connector Signal Multiplexing

D-Type

Connector Pin

PC87351 Pin

Parallel Port

FDC

Signal

I/O

Signal

I/O

195

STB/WRITE

I/O

PD0

I/O

INDEX

PD1

I/O

TRK0

PD2

I/O

PD3

I/O

RDATAI

PD4

I/O

DSKCHG

PD5

I/O

MSEN0

PD6

I/O

DRATE0

PD7

I/O

MSEN1

ACK

DR1

BUSY/WAIT

MTR1

WDATAO

SLCT

WGATE

AFD/DSTRB

I/O

DENSEL

ERR

HDSEL

INIT

I/O

DIR

SLIN/ASTRB

I/O

STEP

18 - 23

GND

98 or 1271

PNF = Ground

PNF = 1

GND

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