PC87351 datasheet(12/86 Pages) NSC

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1.0 Signal/Pin Connection and Description (Continued)

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1.2

SIGNAL/PIN DIRECTORY

See Table 1-2 for an alphabetical listing of all signals, cross-referenced to additional information for detailed functional de-

scriptions, electrical DC characteristics, and pin multiplexing. The DC characteristics are denoted by a buffer type symbol,

described briefly in Table 1-1 and in detail in Sections 11.1.6 to 11.1.10. The pin multiplexing information refers to three dif-

ferent types of multiplexing:

• MUX - Multiplexed functions. Pins are shared between two different functions. Each function is associated with different

board connectivity, and normally, the function selection is determined by the board design and cannot be changed dynam-

ically. The multiplexing options must be configured by the BIOS upon power-up, in order to comply with the board imple-

mentation.

• MM - Multiple Mode. Pins have two or more modes of operation within the same function. These modes are associated

with the same external (board) connectivity. Mode selection may be controlled by the device driver, through the registers

of the functional block, and do not require a special BIOS setup upon power-up. These pins are not considered multi-

plexed pins from the SuperI/O configuration perspective. The mode selection method (registers and bits) as well as the

signal specification in each mode, are described within the functional description of the relevant functional blocks.

• PPM - Parallel Port MUX. This special multiplexing of the FDC signals on the Parallel Port pins allows connection of the

external FDC through the Parallel Port connector. This multiplexing is dynamic, controlled by hardware, and does not

require any special BIOS setup except for enabling the PPM function. The PPM functionality and a listing of the pins that

are multiplexed are described in Section 2.5.

Table 1-1. Buffer Types

Name

Description

Section

GND

Ground pin

N/A

INPCI

Input, PCI 5V

11.1.5

INSTRP

Input, Strap pin (min VIH is 0.6VDD) with weak pull-down during strap time

11.1.6

INT

Input, TTL compatible

11.1.7

INTS

Input, TTL compatible with Schmitt trigger

11.1.8

INULR

Input, with serial UL Resistor

N/A

Op/n

Output, Totem-Pole buffer that is capable of sourcing

p mA and sinking n mA 11.1.9

ODn

Output, Open-Drain output buffer that is capable of sinking

n mA

11.1.10

PWR

Power pin

N/A

Table 1-2. Signal/Pin Directory

Signal

Pin/s

Functional Group

DC Characteristics

Multiplexed

Name

Section

Buffer Type

Section

A15-0

28-19, 16-11 Host Interface

1.4.5

INT

11.1.7

ACK

Parallel Port

1.4.8

INT

11.1.7

PPM

AEN

Host Interface

1.4.5

INT

11.1.7

AFD/DSTRB

Parallel Port

1.4.8

OD14, O14/14 11.1.10, 11.1.9

MM/PPM

ASTRB

See SLIN/ASTRB

BADDR

110

Strapping

1.4.11

INSTRP

11.1.6

MUX

BOUT1

See DTR1/BOUT1

BOUT2

See DTR2/BOUT2

BUSY/WAIT

Parallel Port

1.4.8

INT

11.1.7

MM/PPM

CLKIN

Clock

1.4.1

INT

11.1.7

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