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PC87351 датащи(PDF) 43 Page - National Semiconductor (TI) |
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PC87351 датащи(HTML) 43 Page - National Semiconductor (TI) |
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43 / 86 page ![]() 2.0 Device Architecture and Configuration (Continued) 43 www.national.com 2.10 SYSTEM WAKE-UP CONTROL (SWC) - LOGICAL DEVICE 4 2.10.1 Configuration 1. The logical device registers are maintained, and all wake-up detection mechanisms are func- tional. Index Configuration Register or Action Type Reset 30h Activate. When bit 0 is cleared, the registers of this logical device are not accessible.1 R/W 00h 60h Base Address MSB Register R/W 00h 61h Base Address LSB Register. Bits 3-0 (for A3-0) are read only, 0000b. R/W 00h 70h Interrupt Number (For routing the PWUREQ signal). R/W 00h 71h Interrupt Type. Bit 1 is read/write. Other bits are read only. R/W 03h 74h Report no DMA assignment RO 04h 75h Report no DMA assignment RO 04h |
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