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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PC87351 датащи(PDF) 46 Page - National Semiconductor (TI) |
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PC87351 датащи(HTML) 46 Page - National Semiconductor (TI) |
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46 / 86 page  2.0 Device Architecture and Configuration (Continued) 46 www.national.com 2.12 GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORTS - LOGICAL DEVICE 7 2.12.1 General Description The GPIO functional block includes 11 pins, arranged in one 8-bit port and one 3-bit port. Both of these ports are standard. The eight runtime registers of these ports are arranged in the GPIO address space shown in Table 2-12. The GPIO base address is 8-byte aligned. Address bits 2-0 are used to indicate the register offset. 2.12.2 Implementation The standard GPIO port has four runtime registers. Each pin is associated with a configuration register that includes seven configuration bits. 2.12.3 Configuration Figure 2-6 describes the organization of these registers. Table 2-12. Runtime Registers in GPIO Address Space Offset Mnemonic Name Reset Port Type 00h GPDO1 GPIO Data Out 1 Register FFh 1 R/W 01h GPDI1 GPIO Data In 1 Register XXh RO 02h GPIEN1 GPIO Interrupt Enable 1 Register 00h R/W 03h GPST1 GPIO Status 1 Register 00h R/W1C 04h GPDO2 GPIO Data Out 2 Register 07h 2 R/W 05h GPDI2 GPIO Data In 2 Register 0Xh RO 06h GPIEN2 GPIO Interrupt Enable 2 Register 00h R/W 07h GPST2 GPIO Status 2 Register 00h R/W1C Index Configuration Register or Action Type Reset 30h Activate. See also bit 0 of the SIOCF1 Register. R/W 00h 60h Base Address MSB Register R/W 00h 61h Base Address LSB Register. Bits 2-0 (for A2-0) are read only, 000b. R/W 00h 70h Interrupt Number (For routing the IRQ from the GPIO). R/W 00h 71h Interrupt Type. Bit 1 is read/write. Other bits are read only. R/W 03h 74h Report no DMA assignment R 04h 75h Report no DMA assignment R 04h F0h GPIO Pin Configuration Select Register R/W 00h F1h GPIO Pin Configuration Access Register R/W 00h |
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