LAN89730 datasheet(112/218 Pages) MICROCHIP

112 / 218 page

LAN89730

DS60001348A-page 112

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4.13.4

SOFT RESET (SRST)

A Soft reset is initiated by writing a ‘1’ to bit 0 of the HW_CFG register (SRST). This self-clearing bit will return to ‘0’ after

approximately 2 µs, at which time the Soft Reset is complete. Soft reset does not clear control register bits marked as

NASR.

Writing SRST = 1 will cause the device to disconnect from the USB shortly after the first good OUT Data packet during

the Data Phase. A brief delay will allow enough time for the device to send the ACK for the Data Stage, but the device

will be disconnected (causing a 3-strikes time-out failure) for any next transaction (e.g., the Status Stage, or a repeated

Data Stage, if there were any bus errors). To the USB host, the aforementioned behaviors are the same as what hap-

pens during any surprise removal of a USB Device. This behavior is completely normal, and a compliant host must be

tolerant of it.

4.13.5

USB RESET

A USB reset causes a reset of the entire chip with the exception of the USB Device Controller and the HSIC interface

(UDC, parts of the CTL, and the HSIC interface). The PLL is not turned off. It will occur after a POR, nRESET, or SRST

(these will all force disconnects of the USB bus). After a USB reset, the READY bit in the PMT_CTRL register can be

read by the host and will read back a ‘0’ until the EEPROM contents are loaded (provided one is present). Upon com-

pletion of the EEPROM contents load, the READY bit in PMT_CTRL is set high, and the device can be configured via

its control registers.

4.13.6

PHY SOFTWARE RESET

The Ethernet PHY can be reset via two software-initiated resets. Refer to Section 4.6.9, "PHY Resets" for details.

4.13.7

NTRST

This active-low reset is used by the TAP controller.

4.14

Configuration Straps

Configuration straps are multi-function pins that are driven as outputs during normal operation. During a Power on Reset

(POR) or a External Chip Reset (nRESET), these outputs are tri-stated. The high or low state of the signal is latched

following de-assertion of the reset and is used to determine the default configuration of a particular feature. Configura-

tion strap signals are noted in Chapter 2, "Pin Description and Configuration".

Configuration straps are latched as a result of a Power on Reset (POR) or a External Chip Reset (nRESET). Configu-

ration straps include internal resistors in order to prevent the signal from floating when unconnected. If a particular con-

figuration strap is connected to a load, an external pull-up or pull-down should be used to augment the internal resistor

to ensure that it reaches the required voltage level prior to latching. The internal resistor can also be overridden by the

addition of an external resistor.

Note:

The EEPROM contents are reloaded by this reset.

Note:

After the assertion of the SRST the internal Ethernet PHY is put into General Power-Down mode.

Note:

This reset does not cause the USB contents from the EEPROM to be reloaded. Only the MAC address is

reloaded.

Note:

After the assertion of the USB Reset the internal Ethernet PHY is put into General Power-Down mode.

Note:

The system designer must guarantee that configuration straps meet the timing requirements specified in

Section 7.6.4, "Reset and Configuration Strap Timing" and Section 7.6.3, "Power-On Configuration Strap

Valid Timing". If configuration straps are not at the correct voltage level prior to being latched, the device

may capture incorrect strap values

Note:

Configuration straps must never be driven as inputs. If required, configuration straps can be augmented,

or overridden with external resistors.

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