LAN89730 datasheet(79/218 Pages) MICROCHIP

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DS60001348A-page 79

LAN89730

4.6.2.2

Equalizer, Baseline Wander Correction and Clock and Data Recovery

The 6 bits from the ADC are fed into the DSP block. The equalizer in the DSP section compensates for phase and ampli-

tude distortion caused by the physical channel consisting of magnetics, connectors, and CAT- 5 cable. The equalizer

can restore the signal for any good-quality CAT-5 cable between 1 m and 150 m.

If the DC content of the signal is such that the low-frequency components fall below the low frequency pole of the iso-

lation transformer, then the droop characteristics of the transformer will become significant and Baseline Wander (BLW)

on the received signal will result. To prevent corruption of the received data, the PHY corrects for BLW and can receive

the ANSI X3.263-1995 FDDI TP-PMD defined “killer packet” with no bit errors.

The 100M PLL generates multiple phases of the 125 MHz clock. A multiplexer, controlled by the timing unit of the DSP,

selects the optimum phase for sampling the data. This is used as the received recovered clock. This clock is used to

extract the serial data from the received signal.

4.6.2.3

NRZI and MLT-3 Decoding

The DSP generates the MLT-3 recovered levels that are fed to the MLT-3 converter. The MLT-3 is then converted to an

NRZI data stream.

4.6.2.4

Descrambling

The descrambler performs an inverse function to the scrambler in the transmitter and also performs the Serial In Parallel

Out (SIPO) conversion of the data.

During reception of IDLE (/I/) symbols, the descrambler synchronizes its descrambler key to the incoming stream. Once

synchronization is achieved, the descrambler locks on this key and is able to descramble incoming data.

Special logic in the descrambler ensures synchronization with the remote PHY by searching for IDLE symbols within a

window of 4000 bytes (40 µs). This window ensures that a maximum packet size of 1514 bytes, allowed by the IEEE

802.3 standard, can be received with no interference. If no IDLE-symbols are detected within this time-period, receive

operation is aborted and the descrambler re-starts the synchronization process.

The descrambler can be bypassed by setting bit 0 of register 31.

4.6.2.5

Alignment

The de-scrambled signal is then aligned into 5-bit code-groups by recognizing the /J/K/ Start-of-Stream Delimiter (SSD)

pair at the start of a packet. Once the code-word alignment is determined, it is stored and utilized until the next start of

frame.

4.6.2.6

5B/4B Decoding

The 5-bit code-groups are translated into 4-bit data nibbles according to the 4B/5B table. The SSD, /J/K/, is translated

to “0101 0101” as the first 2 nibbles of the MAC preamble. Reception of the SSD causes the PHY to assert the internal

RX_DV signal, indicating that valid data is available on the Internal RXD bus. Successive valid code-groups are trans-

lated to data nibbles. Reception of either the End of Stream Delimiter (ESD) consisting of the /T/R/ symbols, or at least

two /I/ symbols causes the PHY to de-assert the internal carrier sense and RX_DV.

These symbols are not translated into data.

4.6.2.7

Receiver Errors

During a frame, unexpected code-groups are considered receive errors. Expected code groups are the DATA set (0

through F), and the /T/R/ (ESD) symbol pair. When a receive error occurs, the internal MII’s RX_ER signal is asserted

and arbitrary data is driven onto the internal receive data bus (RXD) to the MAC. Should an error be detected during the

time that the /J/K/ delimiter is being decoded (bad SSD error), RX_ER is asserted and the value 1110b is driven onto

the internal receive data bus (RXD) to the MAC. Note that the internal MII’s data valid signal (RX_DV) is not yet asserted

when the bad SSD occurs.

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