LAN89730 datasheet(111/218 Pages) MICROCHIP

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 2013-2015 Microchip Technology Inc.

DS60001348A-page 111

LAN89730

4.13

Resets

The device has the following chip level reset sources:

• Power on Reset (POR)

• External Chip Reset (nRESET)

• Lite Reset (LRST)

• Soft Reset (SRST)

• USB Reset

• PHY Software Reset

• nTRST

4.13.1

POWER ON RESET (POR)

A Power on Reset occurs whenever power is initially applied to the device, or if power is removed and reapplied to the

device. A timer within the device will assert the internal reset for approximately 22 ms.

4.13.2

EXTERNAL CHIP RESET (NRESET)

A hardware reset will occur when the nRESET pin is driven low. The READY bit in the PMT_CTRL register can be read

by the host, and will read back a ‘0’ until the hardware reset is complete. Upon completion of the hardware reset, the

READY bit in PMT_CTRL is set high.

After the READY bit is set, the device can be configured via its control registers. The nRESET pin is pulled-high inter-

nally by the device and can be left unconnected if unused. If used, nRESET must be driven low for a minimum period

as defined in Section 7.6.4, "Reset and Configuration Strap Timing". If nRESET is unused, the device must be reset

following power-up via a soft reset (SRST).

4.13.3

LITE RESET (LRST)

This reset is initiated via the LRST bit in the Section 6.3.5, "Hardware Configuration Register (HW_CFG)". It will reset

the entire chip with the exception of the USB Device Controller and the USB PHY (UDC, parts of the CTL, and the HSIC

interface). The PLL is not turned off.

Note:

The EEPROM contents are loaded by this reset.

Note:

After the assertion of the POR, the internal Ethernet PHY is put into general power down mode.

Note:

While the internal Power on Reset circuitry may assert during brown-out conditions, this is not guaranteed.

For proper operation in applications where brown-outs may occur, use of an external reset circuit is recom-

mended.

Note:

After the assertion of nRESET, the internal Ethernet PHY is put into General Power-Down mode.

Note:

For proper operation in applications where brown-outs may occur, use of an external reset circuit is recom-

mended.

Note:

This reset does not cause the USB contents from the EEPROM to be reloaded.

Note:

This reset does not place the device into the Unconfigured state.

Note:

After the LRST, the USB pipes corresponding to the Bulk-In, Bulk-Out, and Interrupt Endpoints must be

reset. This process entails clearing the device’s ENDPOINT_HALT feature and resetting the data toggle on

the host side.

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