LAN89730 datasheet(12/218 Pages) MICROCHIP

12 / 218 page

LAN89730

DS60001348A-page 12

 2013-2015 Microchip Technology Inc.

TABLE 2-1:

MII INTERFACE PINS

Num Pins

Name

Symbol

Buffer

Type

Description

Receive Error

(Internal PHY

Mode)

RXER

IS/O8

(PD)

In Internal PHY Mode, this pin can be configured

to display the respective internal MII signal. Refer

to the Internal MII Visibility Enable (IME) bit of the

Hardware Configuration Register (HW_CFG) on

page 123 for additional information.

Receive Error

(External

PHY Mode)

RXER

(PD)

In External PHY Mode, the signal on this pin is

input from the external PHY and indicates a

receive error in the packet.

Transmit

Enable

(Internal PHY

Mode)

TXEN

IS/O8

(PD)

In Internal PHY Mode, this pin can be configured

to display the respective internal MII signal. Refer

to the Internal MII Visibility Enable (IME) bit of the

Hardware Configuration Register (HW_CFG) on

page 123 for additional information.

Transmit

Enable

(External

PHY Mode)

TXEN

(PD)

In External PHY Mode, this pin functions as an

output to the external PHY and indicates valid

data on TXD[3:0].

Receive Data

Valid

(Internal PHY

Mode)

RXDV

IS/O8

(PD)

In Internal PHY Mode, this pin can be configured

to display the respective internal MII signal. Refer

to the Internal MII Visibility Enable (IME) bit of the

Hardware Configuration Register (HW_CFG) on

page 123 for additional information.

Receive Data

Valid

(External

PHY Mode)

RXDV

(PD)

In External PHY Mode, the signal on this pin is

input from the external PHY and indicates valid

data on RXD[3:0].

Receive

Clock

(Internal PHY

Mode)

RXCLK

IS/O8

(PD)

In Internal PHY Mode, this pin can be configured

to display the respective internal MII signal. Refer

to the Internal MII Visibility Enable (IME) bit of the

Hardware Configuration Register (HW_CFG) on

page 123 for additional information.

Receive

Clock

(External

PHY Mode)

RXCLK

(PD)

In External PHY Mode, this pin is the receiver

clock input from the external PHY.

Transmit

Clock

(Internal PHY

Mode)

TXCLK

IS/O8

(PU)

In Internal PHY Mode, this pin can be configured

to display the respective internal MII signal. Refer

to the Internal MII Visibility Enable (IME) bit of the

Hardware Configuration Register (HW_CFG) on

page 123 for additional information.

Transmit

Clock

(External

PHY Mode)

TXCLK

(PU)

In External PHY Mode, this pin is the transmitter

clock input from the external PHY.

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