LAN89730 datasheet(29/218 Pages) MICROCHIP

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 2013-2015 Microchip Technology Inc.

DS60001348A-page 29

LAN89730

4.0

FUNCTIONAL DESCRIPTION

4.1

Functional Overview

The LAN89730 USB 2.0 to 10/100 Ethernet Controller consists of the following major functional blocks:

• HSIC Interface

• USB 2.0 Device Controller (UDC)

• FIFO Controller (FCT) and Associated SRAM

• 10/100 Ethernet MAC

• 10/100 Internal Ethernet PHY

• IEEE 1149.1 Tap Controller

• EEPROM Controller (EPC)

The following sections discuss the features of each block. A block diagram of the device is shown in Figure 1-1.

4.2

HSIC Interface

The HSIC interface is compliant with the High-Speed Interchip USB Electrical Specification Revision 1.0. High-Speed

Inter-Chip (HSIC) is a digital interconnect bus that enables the use of USB technology as a low-power chip-to-chip inter-

connect at speeds up to 480 Mb/s.

4.3

USB 2.0 Device Controller (UDC)

The USB functionality in the device consists of five major parts. The HSIC interface (discussed in Section 4.2), UCB

(USB Common Block), UDC (USB Device Controller), URX (USB Bulk-Out Receiver), UTX (USB Bulk-In Receiver), and

CTL (USB Control Block). They are represented as the HSIC interface and UDC, collectively, in Figure 1-1.

The UCB generates various clocks, including the system clocks of the device. The URX and UTX implement the Bulk-

Out and Bulk-In Endpoints respectively. The CTL manages control and interrupt Endpoints.

The UDC is a USB low-level protocol interpreter. The UDC controls the USB bus protocol, packet generation/extraction,

PID/Device ID parsing, and CRC coding/decoding with autonomous error handling. It is capable of operating either in

USB 1.1 or 2.0 compliant modes. It has autonomous protocol handling functions such as stall condition clearing on setup

packets, suspend/resume/reset conditions, and remote wakeup. It also autonomously handles error conditions such as

retry for CRC errors, Data toggle errors, and generation of NYET, STALL, ACK and NACK, depending on the Endpoint

buffer status.

The UDC is configured to support one configuration, one interface, one alternate setting, and four Endpoints.

4.3.1

SUPPORTED ENDPOINTS

Table 4-1 lists the supported Endpoints. The following subsections discuss these Endpoints in detail.

The URX and UTX implement the Bulk-Out and Bulk-In Endpoints, respectively. The CTL manages the Control and

Interrupt Endpoints.

TABLE 4-1:

SUPPORTED ENDPOINTS

Endpoint Number

Description

Control Endpoint

Bulk-In Endpoint

Bulk-Out Endpoint

Interrupt Endpoint

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