LAN89730 datasheet(71/218 Pages) MICROCHIP

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 2013-2015 Microchip Technology Inc.

DS60001348A-page 71

LAN89730

The RXCOE supports a maximum of two VLAN tags. If there are more than two VLAN tags, the VLAN protocol identifier

for the third tag is treated as an Ethernet type field. The checksum calculation will begin immediately after the type field.

The RXCOE resides in the RX path within the MAC. As the RXCOE receives an Ethernet frame, it calculates the 16-bit

checksum. The RXCOE passes the Ethernet frame to the RX FIFO with the checksum appended to the end of the frame.

The RXCOE inserts the checksum immediately after the last byte of the Ethernet frame and before it transmits the status

word. The packet length field in the RX Status Word (refer to Section 4.4.1.2) will indicate that the frame size has

increased by two bytes to accommodate the checksum.

Setting the RXCOE_EN bit in the Checksum Offload Engine Control Register (COE_CR) enables the RXCOE, while the

RXCOE_MODE bit selects the operating mode. When the RXCOE is disabled, the received data is simply passed

through the RXCOE unmodified.

FIGURE 4-14:

ETHERNET FRAME WITH VLAN TAG AND SNAP HEADER

FIGURE 4-15:

ETHERNET FRAME WITH MULTIPLE VLAN TAGS AND SNAP HEADER

Note:

When enabled, the RXCOE calculates a checksum for every received frame.

Note:

Software applications must stop the receiver and flush the RX data path before changing the state of the

RXCOE_EN or RXCOE_MODE bits.

Note:

When the RXCOE is enabled, automatic pad stripping must be disabled (bit 8 (PADSTR) of the MAC Con-

trol Register (MAC_CR)) and vice versa. These functions cannot be enabled simultaneously.

DST

SRC

L3 Packet

{DSAP, SSAP, CTRL,

OUI[23:16]}

{OUI[15:0], PID[15:0]}

Calculate Checksum

1DWORD

DST

SRC

L3 Packet

{DSAP, SSAP, CTRL,

OUI[23:16]}

{OUI[15:0], PID[15:0]}

Calculate Checksum

1DWORD

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