LAN89730 datasheet(14/218 Pages) MICROCHIP

14 / 218 page

LAN89730

DS60001348A-page 14

 2013-2015 Microchip Technology Inc.

Management

Clock

(Internal PHY

Mode)

MDC

IS/O8

(PU)

In Internal PHY Mode, this pin can be configured

to display the respective internal MII signal. Refer

to the Internal MII Visibility Enable (IME) bit of the

Hardware Configuration Register (HW_CFG) on

page 123 for additional information.

Management

Clock

(External

PHY Mode)

MDC

(PD)

In External PHY Mode, this pin outputs the man-

agement clock to the external PHY.

General Pur-

pose I/O 2

(Internal PHY

Mode Only)

GPIO2

IS/O8/

OD8

(PU)

This General Purpose I/O pin is fully programma-

ble as either a push-pull output, an open-drain

output or a Schmitt-triggered input.

1Transmit Data

(Internal PHY

Mode)

TXD3

IS/O8

(PU)

In Internal PHY Mode, this pin can be configured

to display the respective internal MII signal. Refer

to the Internal MII Visibility Enable (IME) bit of the

Hardware Configuration Register (HW_CFG) on

page 123 for additional information.

Transmit Data

(External

PHY Mode)

TXD3

(PU)

In External PHY Mode, this pin functions as the

transmit data 3 output to the external PHY.

General Pur-

pose I/O 7

(Internal PHY

Mode Only)

GPIO7

IS/O8/

OD8

(PU)

This General Purpose I/O pin is fully programma-

ble as either a push-pull output, an open-drain

output or a Schmitt-triggered input.

Note:

GPIO7 may provide additional external

PHY Link Up related functionality. Refer

to Section 4.12.2.4, "Enabling External

PHY Link Up Wake Events" for

additional information.

HSIC Output

Impedance

Configuration

Strap

50DRIVER_EN

(PU)

The 50DRIVER_EN strap selects the driver out-

put impedance for the HSIC_DATA and

HSIC_STROBE pins.

0 = 40 Ω output impedance

1 = 50 Ω output impedance

See Note 2-1 for more information on configura-

tion straps.

TABLE 2-1:

MII INTERFACE PINS (CONTINUED)

Num Pins

Name

Symbol

Buffer

Type

Description

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