LAN91C111 datasheet(12/125 Pages) MICROCHIP

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LAN91C111

DS00002276A-page 12

 2011-2016 Microchip Technology Inc.

Asynchronous

Ready

ARDY

OD16

Open drain output. ARDY may be used

when interfacing asynchronous buses to

extend accesses. Its rising (access

completion) edge is controlled by the

XTAL1 clock and, therefore,

asynchronous to the host CPU or bus

clock. ARDY is negated during

Asynchronous cycle when one of the

following conditions occurs:

No_Wait Bit in the Configuration Register

is cleared.

Read FIFO contains less than 4 bytes

when read.

Write FIFO is full when write.

nSynchronous

Ready

nSRDY

O16

Output. This output is used when

interfacing synchronous buses and

nVLBUS=0 to extend accesses. This

signal remains normally inactive, and its

falling edge indicates completion. This

signal is synchronous to the bus clock

LCLK.

nReady Return

nRDYRTN

I**

Input. This input is used to complete

synchronous read cycles. In EISA burst

mode it is sampled on falling LCLK

edges, and synchronous cycles are

delayed until it is sampled high.

Interrupt

INTR0

O24

Interrupt Output – Active High, it’s used to

interrupt the Host on a status event. Note:

The selection bits used to determined by

the value of INT SEL 1-0 bits in the

Configuration Register are no longer

required and have been set to reserved in

this revision of the FEAST family of

devices.

nLocal Device

nLDEV

O16

Output. This active low output is asserted

when AEN is low and A4-A15 decode to

the LAN91C111 address programmed

into the high byte of the Base Address

decode of unlatched address and AEN

signals.

nRead Strobe

nRD

IS**

Input. Used in asynchronous bus

interfaces.

nWrite Strobe

nWR

IS**

Input. Used in asynchronous bus

interfaces.

nData Path

Chip Select

nDATACS

I with

pullup**

Input. When nDATACS is low, the Data

Path can be accessed regardless of the

values of AEN, A1-A15 and the content of

the BANK SELECT Register. nDATACS

provides an interface for bursting to and

from the LAN91C111 32 bits at a time.

EEPROM Clock

EESK

Output. 4

sec clock used to shift data in

and out of the serial EEPROM.

EEPROM

Select

EECS

Output. Serial EEPROM chip select.

Used for selection and command framing

of the serial EEPROM.

Pin No.

Name

Symbol

Buffer

Type

Description

TQFP

QFP

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