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LAN91C111 датащи(PDF) 65 Page - Microchip Technology

номер детали LAN91C111
подробное описание детали  10/100 Non-PCI Ethernet Single Chip MAC PHY
PDF  125 Pages
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производитель  MICROCHIP [Microchip Technology]
домашняя страница  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

LAN91C111 датащи(HTML) 65 Page - Microchip Technology

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LAN91C111
DS00002276A-page 66
 2011-2016 Microchip Technology Inc.
PHY Register Description:
D[15:0]
Register 0
Control
Register 1
Status
Register 2
PHY ID#1
Register 3
PHY ID#2
Register 4
Auto-Negotiation Advertisement
Register 5
Auto-Negotiation Remote End Capability
Register 16
Configuration 1
Register 17
Configuration 2
Register 18
Status Output
Register 19
Mask
Register 20
Reserved
TABLE 9-1:
MII SERIAL FRAME STRUCTURE
<Idle>
<Start>
<Read>
<Write>
<PHY Addr.>
<REG.Addr.>
<Turnaround>
<Data>
IDLE
ST[1:0]
READ
WRITE
PHYAD[4:0]
REGAD[4:0]
TA[1:0]
D[15:0]
Symbol
Name
Definition
R/W
IDLE
Idle Pattern
These bits are an idle pattern. Device will not initiate an MI cycle until
it detects at least 32 1's
W
ST1
ST0
Start Bits
When ST[1:0]=01, a MI Serial Port access cycle starts.
W
READ
Read Select
1 = Read Cycle
W
WRITE
Write Select
1 = Write Cycle
W
PHYAD[4:0]
Physical
Device
Address
PHYSICAL ADDRESS
R
REGAD[4:0]
Register
Address
If REGAD[4:0] = 00000-11110, these bits determine the specific
register from which D[15:0] is read/written. If multiple register access
is enabled and REGAD[4:0] = 11111, all registers are read/written in
a single cycle.
W



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