LAN91C111 datasheet(48/125 Pages) MICROCHIP

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LAN91C111

DS00002276A-page 48

 2011-2016 Microchip Technology Inc.

LS2B, LS1B, LS0B – LED select Signal Enable. These bits define what LED control signals are routed to the LEDB

output pin on the LAN91C111 Ethernet Controller. The default is 10/100 Link detected.

Reserved – Must be 0.

8.11

Bank 1 - Configuration Register

The Configuration Register holds bits that define the adapter configuration and are not expected to change during run-

time. This register is part of the EEPROM saved setup.

EPH Power EN - Used to selectively power transition the EPH to a low power mode. When this bit is cleared (0), the

Host will place the EPH into a low power mode. The Ethernet MAC will gate the 25Mhz TX and RX clock so that the

Ethernet MAC will no longer be able to receive and transmit packets. The Host interface however, will still be active

allowing the Host access to the device through Standard IO access. All LAN91C111 registers will still be accessible.

However, status and control will not be allowed until the EPH Power EN bit is set AND a RESET MMU command is

initiated.

NO WAIT - When set, does not request additional wait states. An exception to this are accesses to the Data Register if

not ready for a transfer. When clear, negates ARDY for two to three clocks on any cycle to the LAN91C111.

LS2B

LS1B

LS0B

LED Select Signal – LEDB

nPLED3+ nPLED0 – Logical OR of 100Mbps Link detected 10Mbps Link detected

(default)

Reserved

nPLED0 - 10Mbps Link detected

nPLED1 – Full Duplex Mode enabled

nPLED2 – Transmit or Receive packet occurred

nPLED3 - 100Mbps Link detected

nPLED4 - Receive packet occurred

nPLED5 - Transmit packet occurred

OFFSET

NAME

TYPE

SYMBOL

CONFIGURATION

READ/WRITE

HIGH

BYTE

EPH

Power

Reserved

WAIT

Reserved

GPCNTRL

EXT PHY

Reserved

LOW

BYTE

Reserved

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