LAN91C111 datasheet(29/125 Pages) MICROCHIP

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DS00002276A-page 29

LAN91C111

is used to sense the actual data transitions once the signal is determined to be valid. The output of the squelch compar-

ator goes to the squelch circuit and is also used for link pulse detection, SOI detection, and reverse polarity detection;

the output of the zero crossing comparator is used for clock and data recovery in the Manchester decoder.

7.7.8.3

TP Squelch - 100 Mbps

The squelch block determines if the TP input contains valid data. The 100 Mbps TP squelch is one of the criteria used

to determine link integrity. The squelch comparators compare the TP inputs against fixed positive and negative thresh-

olds, called squelch levels. The output from the squelch comparator goes to a digital squelch circuit which determines

if the receive input data on that channel is valid. If the data is invalid, the receiver is in the squelched state. If the input

voltage exceeds the squelch levels at least 4 times with alternating polarity within a 10

S interval, the data is considered

to be valid by the squelch circuit and the receiver now enters into the unsquelch state. In the unsquelch state, the receive

threshold level is reduced by approximately 30% for noise immunity reasons and is called the unsquelch level. When

the receiver is in the unsquelch state, then the input signal is deemed to be valid. The device stays in the unsquelch

state until loss of data is detected. Loss of data is detected if no alternating polarity unsquelch transitions are detected

during any 10

S interval. When the loss of data is detected, the receive squelch is turned on again.

7.7.8.4

TP Squelch, 10 Mbps

The TP squelch algorithm for 10 Mbps mode is identical to the 100 Mbps mode except, (1) the 10 Mbps TP squelch

algorithm is not used for link integrity but to sense the beginning of a packet, (2) the receiver goes into the unsquelch

state if the input voltage exceeds the squelch levels for three bit times with alternating polarity within a 50-250 nS inter-

val, (3) the receiver goes into the squelch state when idle is detected, (4) unsquelch detection has no affect on link integ-

FIGURE 7-5:

TP INPUT VOLTAGE TEMPLATE -10MBPS

3.1V

a. Short Bit

585mV

585 mV sin (

t/PW)

Slope 0.5 V/ ns

3.1V

b. Long Bit

585mV

585 mV sin [2

(t - PW/2)/PW]

PW/4

3PW/4

Slope 0.5 V/ ns

585 mV sin (2

t/PW)

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