LAN91C111 datasheet(94/125 Pages) MICROCHIP

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DS00002276A-page 95

LAN91C111

Latched W-R

combined with

nCMD

nWR

I/O Write strobe - asynchronous write access. Address is valid

before leading edge . Data latched on trailing edge. Must not be

active during DMA bursts if DMA is supported.

nSTART

nADS

Address strobe is connected to EISA nSTART.

RESDRV

RESET

nBE0 nBE1 nBE2

nBE3

nBE0 n BE1 nBE2

nBE3

Byte enables. Latched on nADS rising edge.

IRQn

INTR0

Interrupts used as active high edge triggered

D0-D31

32 bit data bus. The bus byte(s) used to access the device are a

function of nBE0-nBE3:

Not used = tri-state on reads, ignored on writes. Note that nBE2 and

nBE3 override the value of A1, which is tied low in this application.

Other combinations of nBE are not supported by the LAN91C111.

Software drivers are not anticipated to generate them.

nEX32

nNOWS

(optional additional

logic)

nLDEV

nLDEV is a totem pole output. nLDEV is active on valid decodes of

LAN91C111 pins A15-A4, and AEN=0. nNOWS is similar to nLDEV

except that it should go inactive on nSTART rising. nNOWS can be

used to request compressed cycles (1.5 BCLK long, nRD/nWR will

be 1/2 BCLK wide).

THE FOLLOWING SIGNALS SUPPORT SLAVE DMA TYPE "C" BURST CYCLES

BCLK

LCLK

EISA Bus Clock. Data transfer clock for DMA bursts.

nDAK<n>

nDATACS

DMA Acknowledge. Active during Slave DMA cycles. Used by the

LAN91C111 as nDATACS direct access to data path.

nIORC

W/nR

Indicates the direction and timing of the DMA cycles. High during

LAN91C111 writes, low during LAN91C111 reads.

nIOWC

nCYCLE

Indicates slave DMA writes.

nEXRDY

nRDYRTN

EISA bus signal indicating whether a slave DMA cycle will take place

on the next BCLK rising edge, or should be postponed. nRDYRTN

is used as an input in the slave DMA mode to bring in EXRDY.

UNUSED PINS

VCC

nVLBUS

GND

TABLE 12-3:

EISA 32 BIT SLAVE SIGNAL CONNECTIONS (CONTINUED)

EISA Bus Signal

LAN91C111 Signal

Notes

nBE0

nBE1

nBE2

nBE3

Double word access

Low word access

High word access

Byte 0 access

Byte 1 access

Byte 2 access

Byte 3 access

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