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AP0100CS датащи(PDF) 30 Page - ON Semiconductor

номер детали AP0100CS
подробное описание детали  High-Dynamic Range (HDR) Image Signal Processor (ISP)
PDF  73 Pages
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AP0100CS датащи(HTML) 30 Page - ON Semiconductor

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AP0100CS HDR: Image Signal Processor (ISP)
Output Formatting
AP0100CS/D Rev. 6, Pub. 1/16 EN
30
©Semiconductor Components Industries, LLC,2016.
Note:
Odd means first cycle; even means second cycle.
Figure 18:
8- bit YCbCr Output (YCbCr_422_8_8)
Notes:
1. Cb Y Cr Y by default.
2. cam_port_parallel_msb_align=0x0
Table 13:
YCbCr Output Modes (cam_port_parallel_msb_align=0x0)
Mode
Byte
Pixel i
Pixel i+1
""Notes"
YCbCr_422_8_8
Odd (DOUT[7 :0])
Cbi
Cri
Data range of 0-255 (Y=16-235 and C=16-240)
Even (DOUT [7:0]
Yi
Yi+1
YCbCr_422_10_10
Odd (DOUT [9:0])
Cbi
Cri
Data range of 0-1023 (Y=64-940 and C=64-960)"
Even (DOUT [9:0])
Yi
Yi+1
YCbCr_422_16
Single (DOUT [15:0])
Cbi_Yi
Cri_Yi+1
Data range of 0-255 (Y=16-235 and C=16-240)
Active Video
Y C b Y Cr
Y C b Y Cr
Y C b Y Cr
YC b Y C r
Im age
Im age
HBlank
HBlank
HBlank
Vertical Blanking
YCb Y Cr
Vblank
Im age
Vblank
YCb Y Cr
Im age
YCb Y C r
Y Cb Y Cr
YCb Y Cr
YCb Y Cr
Im age
Im age
H Blank
H Blank
H Blank
00
00
00
00
Cr
Cr
Cr
Line V alid
Fram e V alid
Pix el C loc k
Data[15:8]
Data[7:0]
Line V alid
Fram e V alid
Pix el C loc k
Data[15:8]
Data[7:0]
Line V alid
Fram e V alid
Pix el C loc k
Data[15:8]
Data[7:0]
Porch – 0-255 cycles
Line V alid
F ram e V alid
Pix el C loc k
Data[15:8]
Data[7:0]
Porch – 0-255 cycles
Porch – 0-255 cycles
Porch – 0-255 cycles



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