AP0100CS datasheet(8/73 Pages) ONSEMI

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AP0100CS HDR: Image Signal Processor (ISP)

System Interfaces

AP0100CS/D Rev. 6, Pub. 1/16 EN

©Semiconductor Components Industries, LLC,2016.

ENDLO

Input

Regulator enable (VDD_REG domain)

SPI_SCLK

Output

Clock output for interfacing to an external SPI flash or EEPROM memory.

SPI_SDI

Input/PU

Data in from SPI flash or EEPROM memory. When no SPI device is fitted, this

signal is used to determine whether the AP0100CS should auto-configure: 0:

Do not auto-configure; Two-wire interface will be used to configure the

device (host-config mode) 1: Auto-configure. This signal has an internal pull-

up resistor.

SPI_SDO

Output

Data out to SPI flash or EEPROM memory.

SPI_CS_BAR

Output

Chip select out to SPI flash or EEPROM memory.

EXT_CLK_OUT

Output

Clock to external sensor.

RESET_BAR_OUT

Output

Reset signal to external signal.

M_SCLK

Output

Two-wire serial interface clock (Master).

M_SDATA

I/O

Two-wire serial interface clock (Master).

FV_IN

Input

Sensor frame valid input.

LV_IN

Input

Sensor line valid input.

PIXCLK_IN

Input

Sensor pixel clock input.

DIN[11:0]

Input

Sensor pixel data input DIN[11:0]

CLK_N

Input

Differential HiSPi clock (sub-LVDS, negative).

CLK_P

Input

Differential HiSPi clock (sub-LVDS, positive).

DATA0_N

Input

Differential HiSPi data, lane 0 (sub-LVDS, negative).

DATA0_P

Input

Differential HiSPi data, lane 0 (sub-LVDS, positive).

DATA1_N

Input

Differential HiSPi data, lane 1 (sub-LVDS, negative).

DATA1_P

Input

Differential HiSPi data, lane 1 (sub-LVDS, positive).

TRIGGER_OUT

Output

Trigger signal for external sensor.

FV_OUT

Output

Host frame valid output (synchronous to PIXCLK_OUT)

LV_OUT

Output

Host line valid output (synchronous to PIXCLK_OUT)

PIXCLK_OUT

Output

Host pixel clock output.

DOUT[15:0]

Output

Host pixel data output (synchronous to PIXCLK_OUT) DOUT[15:0].

DAC_POS

Output

Positive video DAC output in differential mode. Video DAC output in single-

ended mode. This interface is enabled by default using NTSC/PAL signaling.

For applications where composite video output is not required, the video DAC

can be placed in a power-down state under software control.

DAC_NEG

Output

Negative video DAC output in differential mode.

DAC_REF

Output

External reference resistor for Video DAC.

GPIO [5:1]

I/O

General purpose digital I/O.

TRST_BAR

Input

Must be tied to GND in normal operation.

VDDIO_S

Supply

Sensor I/O power supply.

VDDIO_H

Supply

Host I/O power supply.

VDD_PLL

Supply

PLL supply.

VDD

Supply

Core supply.

VDDIO_OTPM

Supply

OTPM power supply.

VDD_DAC

Supply

Video DAC digital power

VDDA_DAC

Supply

Video DAC analog power

VDD_PHY

Supply

PHY IO voltage for HiSPi

Table 3:

Pin Descriptions (Continued)

Name

Type

Description

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