AP0100CS datasheet(61/73 Pages) ONSEMI

61 / 73 page

AP0100CS/D Rev. 6, Pub. 1/16 EN

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

Usage Modes

Notes:

1. VIH/VIL restrictions apply.

2. This is applicable only a when the PLL is bypassed. When the PLL is being used then the user should

ensure that VIH/VIL is met.

Notes:

1. VIL and VIH have min/max limitations specified by absolute ratings.

2. Excludes pins that have internal PU resistors.

Table 34:

AC Electrical Characteristics

Default Setup Conditions: fEXTCLK= 27 MHz, VDDIO_H = VDD_OTPM = 2.8V, VDD_REG = VDDIO_S = 1.8V, VDDA_DAC=3.3V,

VDD_DAC=1.2V; TA = 25°C unless otherwise stated

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Notes

fEXTCLK

External clock frequency

MHz

External input clock rise time

10%-90% VDDIO_H

–

External input clock fall time

90%-10% VDDIO_H

–

DEXTCLK External input clock duty cycle

tJITTER

External input clock jitter

–

500

–

fPIXCLK

Pixel clock frequency (one-clock/pixel)

74.125

MHz

Pixel clock frequency (two-clocks/pixel)

tRPIXCLK Pixel clock rise time (10-90%)

CLOAD=35pf

–

tFPIXCLK Pixel clock fall time (10-90%)

CLOAD=35pf

–

tPD

PIXCLK to data valid

–

tPFH

PIXCLK to FV HIGH

–

tPLH

PIXCLK to LV HIGH

–

tPFL

PIXCLK to FV LOW

–

tPLL

PIXCLK to LV LOW

–

Table 35:

DC Electrical Characteristics

Symbol

Parameter

Condition

Min

Max

Unit

Notes

VIH

Input HIGH voltage

VDDIO_H or VDDIO_S *

0.8

–

VIL

Input LOW voltage

–

VDDIO_H or VDDIO_S *

0.2

IIN

Input leakage current

VIN= 0V or VIN = VDDIO_H

or VDDIO_S

A

VOH

Output HIGH voltage

VDDIO_H or VDDIO_S*

0.80

–

VOL

Output LOW voltage

–

VDDIO_H or VDDIO_S *

0.2

Table 36:

Video DAC Electrical Characteristics

Default Setup Conditions: fEXTCLK= 27 MHz, VDDIO_H = VDD_OTPM = 2.8V, VDD_REG = VDDIO_S = 1.8V,

VDDA_DAC=3.3V, VDD_DAC=1.2V; TA = 25°C unless otherwise stated

Parameter

Symbol

Min

Typ

Max

Unit

Comments

DC Accuracy

Differential Nonlinearity

DNL

±1

LSB

Integral Nonlinearity

INL

±3

LSB

Load Capacitance

CLOAD

At maximum output current

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