AP0100CS datasheet(12/73 Pages) ONSEMI

12 / 73 page

AP0100CS HDR: Image Signal Processor (ISP)

On-Chip Regulator

AP0100CS/D Rev. 6, Pub. 1/16 EN

©Semiconductor Components Industries, LLC,2016.

Power-Up Sequence

Powering up the ISP requires voltages to be applied in a particular order, as seen in

Figure 6. The timing requirements are shown in Table 6. The ISP includes a power-on

reset feature that initiates a reset upon power up of the ISP.

Figure 6:

Power-Up and Power-Down Sequence

Note:

1. When using XTAL the settling time should be taken into account.

Reset

The AP0100CS has three types of reset available:

• A hard reset is issued by toggling the RESET_BAR signal

• A soft reset is issued by writing commands through the two-wire serial interface

• An internal power-on reset

Table 7 on page 13 shows the output states when the part is in various states.

Table 6:

Power-Up and Power-Down Signal Timing

Symbol Parameter

Min

Typ

Max

Unit

Delay from VDDIO_H to VDDIO_S, VDDIO_OTPM, VDDA_DAC, VDD_PHY

(When using HiSPi)

0–

Delay from VDDIO_H to VDD_REG

–

EXTCLK activation

t2 + 1

–

First serial command1

100

–

EXTCLK cycles

EXTCLK cutoff

–

Delay from VDD_REG to VDDIO_H

–

Delay from VDDIO_S, VDDIO_OTPM, VDDA_DAC, VDD_PHY (When using

HiSPi) to VDDIO_H

0–

dv/dt

Power supply ramp time (slew rate)

–

0.1

V/s

VDDIO_H

VDD_REG

EXTCLK

SCLK

SDATA

VDDIO_S, VDDIO_OTPM, VDDA_DAC,

VDD_PHY (when using HiSPi)

dv/dt

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