AP0100CS datasheet(71/73 Pages) ONSEMI

71 / 73 page

AP0100CS/D Rev. 6, Pub. 1/16 EN

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

Two-Wire Serial Register Interface

Figure 49:

Master Two Wire Serial Bus Timing Parameters (CCIM)

Notes:

1. All values referred to VIHmin = 0.9 VDD and VILmax = 0.1VDD levels. EXCLK = 27 MHz.

2. A device must internally provide a hold time of at least 300 ns for the M_SDATA signal to bridge the

undefined region of the falling edge of M_SCLK.

3. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of

the M_SCLK signal.

4. Cb = total capacitance of one bus line in pF.

Table 47:

Master Two-Wire Serial Bus Characteristics (CCIM)

Default Setup Conditions: fEXTCLK = 27 MHz; VDDIO_H = VDD_OTPM = 2.8V; VDD_REG = VDDIO_S = 1.8V; VDDA_DAC=

3.3V; VDD_DAC = 1.2V; TA = 25°C unless otherwise stated

Parameter

Symbol

Standard-Mode

Fast-Mode

Unit

Min

Max

Min

Max

M_SCLK Clock Frequency

fSCL

100

400

KHz

Hold time (repeated) START condition.

After this period, the first clock pulse is generated

tHD;STA

4.0

0.6

s

LOW period of the M_SCLK clock

tLOW

4.7

1.2

s

HIGH period of the M_SCLK clock

tHIGH

4.0

0.6

s

Set-up time for a repeated START condition

tSU;STA

4.7

0.6

s

Data hold time

tHD;DAT

3.453

00.93

s

Data set-up time

tSU;DAT

250

100

Rise time of both M_SDATA and M_SCLK time (10-90%)

1000

20 + 0.1Cb4

300

Fall time of both M_SDATA and M_SCLK time (10-90%)

300

20 + 0.1Cb4

300

Set-up time for STOP condition

tSU;STO

4.0

0.6

s

Bus free time between a STOP and START condition

tBUF

4.7

1.3

s

Capacitive load for each bus line

400

Serial interface input pin capacitance

CIN_SI

3.3

M_SDATA max load capacitance

CLOAD_SD

M_SDATA pull-up resistor

RSD

1.5

4.7

1.5

4.7

K

tSU;STO

tSU;STA

tHD;STA

tHIGH

tLOW

tSU;DAT

tHD;DAT

SDATA

SCLK

tBUF

tHD;STA

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