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AP0100CS датащи(PDF) 47 Page - ON Semiconductor

номер детали AP0100CS
подробное описание детали  High-Dynamic Range (HDR) Image Signal Processor (ISP)
PDF  73 Pages
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AP0100CS датащи(HTML) 47 Page - ON Semiconductor

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AP0100CS/D Rev. 6, Pub. 1/16 EN
47
©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
Protocol
Sequential WRITE, Start at Random Location
This sequence (Figure 37) starts in the same way as the single WRITE to random location
(Figure 36). Instead of generating a no-acknowledge bit after the first byte of data has
been transferred, the master generates an acknowledge bit and continues to perform
byte writes until “L” bytes have been written. The WRITE is terminated by the master
generating a stop condition.
Figure 37:
Sequential WRITE, Start at Random Location
Slave Address
0
S
A Reg Address[15:8]
Write Data
A
Reg Address[7:0]
A
Write Data
Previous Reg Address, N
Reg Address, M
M+1
M+2
M+1
M+3
A
A
A
Write Data
Write Data
M+L-2
M+L-1
M+L
A
A
P
Write Data
(15:8)
Write Data
(7:0)
Write Data
(15:8)
A
Write Data
(7:0)
A
A
A
A
Write Data
A
Write Data
(15:8)
A
Write Data
(7:0)
A
Write Data
Write Data
(15:8)
A
Write Data
(7:0)



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