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AP0100CS датащи(PDF) 46 Page - ON Semiconductor

номер детали AP0100CS
подробное описание детали  High-Dynamic Range (HDR) Image Signal Processor (ISP)
PDF  73 Pages
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AP0100CS датащи(HTML) 46 Page - ON Semiconductor

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AP0100CS HDR: Image Signal Processor (ISP)
Protocol
AP0100CS/D Rev. 6, Pub. 1/16 EN
46
©Semiconductor Components Industries, LLC,2016.
Sequential READ, Start from Current Location
This sequence (Figure 35) starts in the same way as the single READ from current loca-
tion (Figure 33). Instead of generating a no-acknowledge bit after the first byte of data
has been transferred, the master generates an acknowledge bit and continues to
perform byte reads until “L” bytes have been read.
Figure 35:
Sequential READ, Start from Current Location
Single Write to Random Location
Figure 36 shows the typical WRITE cycle from the host to the AP0100CS.The first 2 bytes
indicate a 16-bit address of the internal registers with most-significant byte first. The
following 2 bytes indicate the 16-bit data.
Figure 36:
Single WRITE to Random Location
A
Read Data
Read Data
Previous Reg Address, N
N+1
N+2
N+L-1
N+L
A
Read Data
Slave Address
A
A
1
A
S
P
Read Data
(15:8)
A
Read Data
(7:0)
A
Read Data
(15:8)
A
Read Data
(7:0)
A
Read Data
(15:8)
A
Read Data
(7:0)
A
Read Data
Read Data
(15:8)
A
Read Data
(7:0)
Slave Address
0
S
A Reg Address[15:8]
A
Reg Address[7:0]
A
P
Previous Reg Address, N
Reg Address, M
M+1
A
A
Write Data



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