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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PC87365 датащи(PDF) 135 Page - National Semiconductor (TI) |
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PC87365 датащи(HTML) 135 Page - National Semiconductor (TI) |
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135 / 215 page  6.0 General-Purpose Input/Output (GPIO) Port (Continued) 135 www.national.com 6.4.6 GPIO Event Enable Register (GPEVEN) Location: Device specific Type: R/W 6.4.7 GPIO Event Status Register (GPEVST) Location: Device specific Type: R/W1C Bit 76543210 Name Event Enable Reset 00000000 Bit Description 7 Event Enable. Bits 7-0 correspond to pins 7-0, respectively. Each bit enables system notification triggering by the corresponding GPIO pin. The bit has no effect on the corresponding Status bit in the GPEVST register. 0: IRQ generation by corresponding GPIO pin masked 1: IRQ generation by corresponding GPIO pin enabled 6 5 4 3 2 1 0 Bit 76543210 Name Status Reset 00000000 Bit Description 7 Status. Bits 7-0 correspond to pins 7-0, respectively. Each bit is an edge detector that is set to 1 by the hardware upon detection of an active edge (i.e. edge that matches the IRQ Polarity bit) on the corresponding GPIO pin. This edge detection is independent of the Event Type or the Event Enable bit in the GPEVEN register. However, the bit may reflect the event status for enabled, edge-trigger event sources. Writing 1 to the Status bit clears it to 0. 0: No active edge detected since last cleared 1: Active edge detected 6 5 4 3 2 1 0 |
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