www.ti.com

REFERENCE DECOUPLING

CLAMP DECOUPLING

INTERNAL BIAS CURRENT SETTING

POWER SUPPLY, GROUNDING, AND DEVICE DECOUPLING

DATA OUTPUT

VSP1221

SLES012A – SEPTEMBER 2001 – REVISED JULY 2004

APPLICATION INFORMATION (continued)

Pins REFP (pin 38) and REFM (pin 39) should be connected to ground by means of decoupling capacitors. A

1-µF ceramic capacitor is recommended for reference decoupling. For better high-frequency decoupling, 0.1 µF

ceramic capacitors may be used in parallel. The decoupling capacitors should be placed as close as possible to

the reference pins.

To decouple the clamp voltage, a 1-µF ceramic capacitor may be connected to CLREF (pin 28). See the

CLPDMsection for further details.

To set the internal bias current, ISET (pin 37) should be connected to ground through a 100-k

Ω resistor.

However, no capacitor should be connected to the ISET pin.

The VSP1221 has several power-supply pins. Each major internal analog block has a dedicated AVDD supply

pin (pins 27, 33, and 40). The DVDD supply pin (pin 17) powers all internal digital circuitry. Both AVDD and

DVDD work with 3-V power supplies. DIVDD and DIGND (pins 13 and 14) supply power to the output digital

driver (D0-D11). DIVDD is independent of DVDD and can be operated from 1.8 V to 3.3 V. This allows the

outputs to interface with digital ASICs requiring different supply voltages

General design practices should apply to the PCB to limit high-frequency transients and noise that are fed back

into the supply lines. This requires adequate bypassing of the supply pins. In the case of power supply

decoupling, 0.1-µF ceramic capacitors are sufficient to keep the impedance low over a wide frequency range.

Since their effectiveness depends largely on the proximity to the individual supply pin, all decoupling capacitors

should be placed as close as possible to the supply pins.

To reduce high-frequency and noise coupling, it is highly recommended to short the digital and analog grounds

immediately outside the package. This can be accomplished by running a low-impedance line under the package

between pins DVSS and AVSS.

It is recommended to keep the capacitive loading on the output data lines as low as possible (typically less than

15 pF). Larger capacitive loads demand higher charging-current surges, which can feed back into the analog

portion of the VSP1221 and affect its performance. If the data lines are long, it is advisable to use external

buffers or latches, which also provides the added benefit of isolating the VSP1221 from any digital noise that

may couple back. In addition, resistors in series with each data line helps in minimizing the surge current. Typical

resistor values are 40-50

Ω .

20