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PGA

VOLTAGE REFERENCE

SERIAL INTERFACE

Standard Functionality

TIMING

SHP, SHD, and ADCCLK

CLPDM

VSP1221

SLES012A – SEPTEMBER 2001 – REVISED JULY 2004

PRINCIPLES OF OPERATION (continued)

VSP1221 has a programmable gain amplifier (PGA) which is composed of analog and digital stages. The total

gain range is 0 dB-36 dB in 0.05-dB steps. The gain can be adjusted by programming the PGA register through

the serial port, see the programmable gain amplifier (PGA) register section.

All the reference voltages and the bias currents used by the device are created by an internal bandgap circuit.

Connecting an external 100-k

Ω resistor from ISET (pin 37) to ground provides the bias current. The voltage at

the ISET pin is 1 V and the reference current is 10 µA (1 V/100 k

Ω). The reference voltages for the ADC are

REFP (2.05 V) and REFM (0.75 V). They are available on pins 38 and 39, respectively. The full-scale range of

the ADC is twice the difference between REFP and REFM. Pins REFP and REFM should be heavily decoupled

with appropriate capacitors (1 µF recommended).

A simple three-wire (SCLK, SDIN, and SLOAD) serial interface is provided to allow writing/reading the internal

registers of the VSP1221. The serial data SDIN (pin 47) is 16 bits long. The MSB (most significant bit) is set to 0

for writing to and to 1 for reading from the internal registers. Following this, there are five address bits for

accessing and ten data bits for writing to the particular registers. During a read operation, data from the particular

register is available on SDO (pin 1). To enable serial read/write, SLOAD (pin 46) should be pulled low. Sending

blocks of 16-bit data to SDIN can program multiple registers. The polarity of the serial clock (SCLK, pin 48) can

be controlled by SCKP (pin 45). For serial interface timing see the serial data format section; for serial data

format and description of the internal registers see the register description section.

A description of the different timing signals of the VSP1221 follows. The timing diagram in the sample and

conversion timing section has additional information. Note that the polarity of SHP/SHD, ADCCLK, CLPDM,

BLKG, and CLPOB can be programmed to be active low or active high (see the signal polarity register section).

The timing diagram in the timing specifications section is based on active-low polarity.

SHP/SHD are used for correlated double sampling of the CCD signal. Sample reference (SHP) is used to sample

the reference level of the CCD signal, and sample data (SHD) is used to sample the data level. The ADC clock

(ADCCLK) is used to latch the output of the ADC to the external pins. SHP, SHD, and ADCCLK are used to

generate internal timing signals using the on-chip timing generator for proper synchronization of different blocks.

SHP, SHD, and ADCCLK can be internally delayed by programming the timing registers through the serial port

(see the timing register 1 and timing register 2 sections.

The following is recommended to get the best performance:

The CCD signal is capacitively coupled to the VSP1221 because the dc level of the CCD signal is usually too

establish the proper dc bias for the CDS. The dc bias for the CDS is set to the clamp voltage, which is around

800 mV below the supply voltage. The clamp voltage can be decoupled with an external capacitor at CLREF (pin

decoupling capacitor. The recommended value for the decoupling capacitor is 1 µF. The dummy pixel clamp

(CLPDM) signal is usually available during the dummy pixels of the CCD and is applied at the line rate of the

CCD sensor.

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