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BLKG

CLPOB

OE

RESET

OPTICAL-BLACK CALIBRATION

VSP1221

SLES012A – SEPTEMBER 2001 – REVISED JULY 2004

PRINCIPLES OF OPERATION (continued)

Some CCDs have large transient output signals during blanking intervals. Such signals might drive the VSP1221

into saturation and can cause long recovery times. To prevent this, the VSP1221 has an input-blanking function

which disconnects the CCD input from the CDS when it receives the blanking (BLKG) signal. Additionally, the

output from the VSP1221 during blanking will be equal to the value programmed in the blanking register. The

blanking level can be adjusted by programming the blanking register through the serial port (see the blanking

register section).

The optical-black clamp (CLPOB) pulse is used for optical-black calibration (explained in the optical-black

calibration section). The CLPOB pulse is given to the device during optical-black pixels of the CCD.

Output enable (OE) is used to latch the output data to the output pins. When OE is low, data is latched to the

output pins (D0-D11); when it is high, the output is 3-state.

When the reset (RESET) signal is pulled low (hardware reset), all the internal registers are reset to their default

values. In addition, the device also has a software-reset option that allows setting the RTSY bit in the control

register through the serial port (see the control register section). See the control register section for the default

values of the internal registers. In addition to resetting the registers, hardware reset also resets the output of the

OB DAC to zero. However, to exactly reset the OB DAC to zero, RESET must be kept low for approximately

600 ns.

Optical-black calibration (OB) is used to clamp the CCD black level to the user-defined OB reference level. In

CCDs, thermally generated electrons produce a significant amount of charge even at room temperature. So,

even in the absence of light (black level), thermal electrons generate a considerable amount of current in CCDs.

Thus, the CCD black level carries a residual signal, also known as the CCD offset, which is typically in the order

of 50 mV. This residual signal reduces the effective dynamic range of the CCD input, resulting in a degradation

of image quality. An offset voltage must be subtracted from the CCD black level so that the difference between

the CCD black level and the offset voltage is equal to the reference OB level programmed by the user. The

reference OB level is much lower than the CCD black level, so that the effective dynamic range of the CCD input

increases and the image quality improves. The offset voltage has to be determined based on the CCD black

level. There are certain CCD pixels which are not exposed to light (optical-black pixels) and the CCD signal

corresponding to these pixels represent the CCD black level. Thus, the offset voltage is determined during the

optical-black pixels, and the offset voltage is kept constant and is subtracted from the CCD input to cancel the

CCD offset during normal image pixels.

OB calibration in the VSP1221 is done in a closed feedback loop. The difference between the CCD black level

and the offset voltage is compared with the user-defined OB reference level at the output of the digital PGA

stage. The error is fed to an OB calibration circuit which generates a step proportional to the error and a sign

based on the sign of the error. The step and the sign are then given to the OB DAC, which generates an analog

voltage that updates the offset voltage at the input of the CDS. If the error is positive, the offset voltage is

increased; if the error is negative, the offset voltage is decreased. This continues in a closed feedback loop until

the difference between the CCD black level and the offset voltage converges to the OB reference level. The OB

calibration circuit has been designed so that a 100-mV CCD black level converges to zeroreference OB level

within 500-750 pixel clocks. Convergence time increases with an increase in gain. Convergence is faster if the

CCD black level is smaller than 100 mV. A plot of the convergence time as a function of the PGA gain is shown

in the performance plots section. Since the feedback loop includes the CDS, the PGA, and the ADC, it also

cancels any offset introduced by these blocks. The OB reference level can be adjusted by programming the OB

register through the serial port (see the OB register section).

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