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Control Register

Programmable-Gain Amplifier (PGA) Register

VSP1221

SLES012A – SEPTEMBER 2001 – REVISED JULY 2004

SD15

SD1

SD1

SD0

SD14

SD12

SD10

SD9

SD8

SD7

SD6

SD5

SD4

SD3

SD2

SD1

MSB

3

1

LSB

RD/W

Re-

Re-

0

0

0

0

0

STBYZ

CLAMPPIN

OB

Reserved

Reserved

RTSY

R

served

served

Address

Data

BIT

NAME

DEFAULT VALUE

DESCRIPTION

SD0

RTSY

0

RTSY = 0, no change

RTSY = 1, reset all register bits to their default settings

SD1

RESERVED

0

Reserved

SD2

RESERVED

0

Reserved

SD3-SD5

RESERVED

All 0

Reserved

SD6

RESERVED

X

Reserved

SD7

OB

1

OB = 1, optical-black calibration enable

SD8

1

CLAMPPIN = 1, disable clamping on PIN (pin 31), connect PIN directly to ground.

CLAMPPIN = 0, enable clamping on PIN (pin 31), connect PIN to ground via capacitor.

SD9

STBYZ

1

STBYZ = 0, device in power-down mode (software power down) STBYZ = 1, no change

(1)

Under this condition, the previous value of black level remains unchanged.

(2)

See the CCD input section.

SD15

SD0

SD14

SD13

SD12

SD11

SD10

SD9

SD8

SD7

SD6

SD5

SD4

SD3

SD2

SD1

MSB

LSB

RD/WR

0

0

0

0

1

MSB

GAIN

LSB

Address

Data

BIT

NAME

DEFAULT VALUE

DESCRIPTION

SD0-DS9

GAIN

All 0

Programmable-gain control

Gain step = 0.05 dB

Minimum gain = 0 dB

Maximum gain = 36 dB

Code

Gain

0000000000

0 dB

0000000001

0.05 dB

.

.

.

1011001111

35.95 dB

1011010000

36 dB

Higher codes

36 dB

11