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PRINCIPLES OF OPERATION

INTRODUCTION

CDS

Analog

PGA

Digital

PGA

12-Bit

OB DAC

Latch

CCD Input

12-Bit

Output

ADCCLK

Gain Code

Gain Code

Input

Clamp

OB

Calibration

Circuit

OB Reference

ADC

CLPDM

SHP

BLKG

SHD

OE

CLPOB

CDS

ADC

VSP1221

SLES012A – SEPTEMBER 2001 – REVISED JULY 2004

The principle functions of the VSP1221 are described below. The sections discussed are:

•

CDS

•

ADC

•

PGA

•

Voltage and current reference

•

Serial interface

•

Timing

– SHP, SHD, AND ADCCLK

– CLPDM

– BLKG

– CLPOB

– OE

– RESET

•

Optical-black calibration

•

Standby mode

•

General-purpose DAC

Before describing the individual blocks, a simplified block diagram of the VSP1221 is shown in Figure 8.

Figure 8. Simplified Block Diagram of the VSP1221

The output signal from the CCD is fed to the correlated double sampler (CDS) through off-chip coupling capacitor

the reference level (SHP) and at the data level (SHD). Subtracting these two samples extracts the pixel value

and reduces the reset noise and other low-frequency noises that are present at the output of the CCD signal.

The output analog signal from the analog PGA stage is passed to the 12-bit analog-to-digital converter (ADC).

The ADC employs a three-stage pipelined architecture to achieve high-throughput and low-power consumption.

Fully-differential implementation and digital-error correction ensures 12-bit resolution.

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