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VSP1221 датащи(PDF) 6 Page - Texas Instruments |
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VSP1221 датащи(HTML) 6 Page - Texas Instruments |
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6 / 26 page ![]() www.ti.com TIMING REQUIREMENTS SAMPLE AND CONVERSION TIMING N N+1 N−10 tWSHD tCCD_SHP SHP SHD ADCCLK tCCD_SHD tDSHD tADCCLK tADC_SHD tWADC tHOLD tOD D0–D11 N−9 N−8 N−7 tWADC DIN (CCD IN) tWSHP tDSHP VSP1221 SLES012A – SEPTEMBER 2001 – REVISED JULY 2004 Figure 2. Sample and Conversion Timing SAMPLE AND CONVERSION TIMING PARAMETERS MIN TYP MAX UNIT tADCCLK ADC clock period 46 ns tWADC ADC high or low width 23 ns tWSHP SHP pulse width 5 ns tWSHD SHD pulse width 5 ns tCCD_SHP CCD reset start to SHP rising edge See Note(1) See Note(1) See Note(1) tCCD_SHD CCD data start to SHD rising edge See Note(2) See Note(2) See Note(2) tADC_SHD ADC falling edge to SHD rising edge 15 35 ns tDSHP Sampling delay, reset 1 1.75 3 ns tDSHD Sampling delay, data 4 5 7 ns tHOLD Output hold time 4 ns tOD Output delay 4 15 ns (1) Best performance if tCCD_SHP > 15 ns Good performance if 10 ns < tCCD_SHP < 15 ns Poor performance if tCCD_SHP < 10 ns (2) Best performance if tCCD_SHD > 19 ns Good performance if 10 ns < tCCD_SHD < 19 ns Poor performance if tCCD_SHD < 15 ns 6 |
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