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SDO Timing

SCLK

SDO

MSB

16 Bits

LSB

Standard Functionality, SCKP (Pin 45) = Low, Operation = Read

MSB

A4 A3 A2 A1 A0

(Address)

CLK CLK

1

2

CLK

6

CLK

7

CLK

16

CLK

17

CLK

18

CLK

19

CLK

23

CLK

24

CLK

32

MSB

D9–D0 LSB

DATA_REQUEST

(16 Bits)

D9–D0

(Data)

LSB

D15–D10

DATA_SEND

(16 Bits)

SLOAD

SCLK

SDIN

SDO

VSP1221

SLES012A – SEPTEMBER 2001 – REVISED JULY 2004

Figure 6. Serial Interface Timing Between SCLK and SDO

PARAMETERS

MIN

TYP

MAX

UNIT

Data output hold time

5

ns

Data output delay

13

ns

(1)

Data output transition occurs at the falling edge of SCLK; so data should be sampled at the rising edge of SCLK. Since the SDO pin is

multiplexed with the D0 pin, OE (pin 42) should be low.

Figure 7. Serial Interface Timing for Read, SCKP = Low

The SDO timing is the same as before, except that data should be sampled at the falling edge of SCLK.

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