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TLV320AIC21 датащи(PDF) 14 Page - Texas Instruments |
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TLV320AIC21 датащи(HTML) 14 Page - Texas Instruments |
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14 / 56 page ![]() www.ti.com TIMING REQUIREMENTS th1 2.4 V MCLK RESET 2.4 V tsu1 2.4 V twL twH td1 td2 td1 td2 ten td3 tdis tsu2 th2 D15 D15 SCLK FS FSD DOUT DIN TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363D – MARCH 2002 – REVISED APRIL 2005 Figure 1. Hardware Reset Timing Figure 2. Serial Communication Timing TEST CONDITIONS MIN TYP MAX UNIT twH Pulse duration, MCLK high 5 twL Pulse duration, MCLK low 5 tsu1 Setup time, RESET, before MCLK high (see Figure 1) 3 th1 Hold time, RESET, after MCLK high (see Figure 1) 2 td1 Delay time, SCLK ↑ to FS/FSD↓ CL = 20 pF 5 ns td2 Delay time, SCLK ↑ to FS/FSD↑ 5 td3 Delay time, SCLK ↑ to DOUT 15 ten Enable time, SCLK ↑ to DOUT 15 tdis Disable time, SCLK ↑ to DOUT 15 tsu2 Setup time, DIN, before SCLK ↓ 10 th2 Hold time, DIN, after SCLK ↓ 10 14 |
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