TLV320AIC21 datasheet(37/56 Pages) TI1

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S/Sr

I2C Device Address (3 Bit)+

SMARTDM Device Address +

R/W

= 0

Mode (5 Bit) + Index

(3 Bit)

Ack

Control Register

Data (Write)

Ack

Control Register

Data (Write)

7 Bit

1 Bit

8 Bit

Increment Index Register Address

Default/Broadcast

(00000/11111)

Write Mode

To the Address Given

by Index Register

Address

To the Address Given

by Index Register

Address

S/Sr I2C Device Address (3 Bit)+

SMARTDM Device Address +

R/W

= 1

Control Register Data

(Read)

Ack

Control Register

Data (Read)

Ack

7 Bit

1 Bit

8 Bit

Read Mode

From the Address Given

by Index Register Address

From the Address Given

by Index Register Address

Increment Index

S/Sr I2C Device Address (3 Bit)+

SMARTDM Device Address +

R/W

= 0

Mode (5 Bit) + Index

(3 Bit)

Ack

7 Bit

1 Bit

8 Bit

For Initializing Index Register Address

Stop

TLV320AIC20, TLV320AIC21

TLV320AIC24, TLV320AIC25

TLV320AIC20K, TLV320AIC24K

SLAS363D – MARCH 2002 – REVISED APRIL 2005

•

S/Sr -> Start/Repeated Start.

Figure 33. Index Register Addresses

Each AIC2x codec consists of 2 channels. Each channel has 6 registers to enable the user to control various

components. Registers that control resources that are common across the two channels are shadowed. This

means that writing to the appropriate register in one channel automatically updates the contents of the same

updates the contents of register 4 for channel 2 and vice versa. Refer to the individual register description for a

more detailed description of the exact register bits that are shadowed. Bits D15 through D13 represent the

control register address that is written with data carried in D7 through D0. Bit D12 determines a read or a write

cycle to the addressed register. When D12 = 0, a write cycle is selected. When D12 = 1, a read cycle is selected.

Bit D11 controls the broadcast mode as described above, in which the broadcast mode is enabled if D11 is set to

1. Always write 1s to the bits D10 through D8.

Table 3 shows the register map.

Table 3. Register Map

D15

D14

D13

D12

D11

D10

Control Register Content

Table 4. Register Addressing

D15

D14

D13

No operation

Control 1

Control 2

Control 3

Control 4

Control 5

Control 6

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