TLV320AIC21 datasheet(30/56 Pages) TI1

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SCLK

DIN

DOUT

64 SCLKS

Data Frame

Control Frame

Slot 0

CH1 16-Bit DAC

Slot 2

CH1 Register Data

CH2 Register Data

Slot 3

CH2 Register Data

Slot 1

CH2 16-Bit DAC

CH1 16-Bit ADC

CH2 16-Bit ADC

SCLK

DIN/

DOUT

2n-1

2n-2

2n-3

Master Slave

n-1

Slave

n-2

Slave

Master

Slave

n-1

Slave

n-2

Slave

Data Frame

Control Frame

(Register R/W)

16 SCLKs Per Slot

Slot

Number

NOTE: n/2 is the total number of AIC20s in the cascade

Continuous Data Transfer Mode

SCLK

32 SCLKS

Data Frame

Slot 0

CH1 16-Bit DAC

CH1 16-Bit ADC

CH2 16-Bit ADC

Slot 0

CH1 16-Bit DAC

Slot 1

CH2 16-Bit DAC

Slot 1

CH2 16-Bit DAC

Data Frame

DIN

DOUT

TLV320AIC20, TLV320AIC21

TLV320AIC24, TLV320AIC25

TLV320AIC20K, TLV320AIC24K

SLAS363D – MARCH 2002 – REVISED APRIL 2005

Figure 23. Programming Mode: Stand-Alone Timing

Figure 24. Standard Operation/Programming Mode: Master-Slave Cascade Timing

The continuous data transfer mode, selected by setting bit D6 of each codec's control register 1 to 1, contains

conversion data only. In continuous data transfer mode, the control frame is eliminated, and the period of FS

signal contains only the data frame in which the 16-bit data is transferred contiguously, with no inactivity between

bits. The control frame can be reactivated by setting the LSB of DIN data to 1 if the data is in the 15+1 format. To

return the programming mode in the 16-bit DAC data format mode, write 0 in bit D6 of each codec's control

2C or S2C, or do a hardware reset to come out of continuous data transfer mode. If continuous

data transfer mode needs to be used with turbo mode, then the codec should first be set in turbo mode before it

is switched from the default programming mode to the continuous data transfer mode.

Figure 25. Standard Operation/Continuous Data Transfer Mode: Stand-Alone Timing

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