TLV320AIC21 datasheet(21/56 Pages) TI1

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Functional Description

Operating Frequencies

MCLK

1/P

1/(MN)

128FS

(devnum x mode)/(MNP)

SCLK

1/(16 x mode x devnum)

en_dll

Digital

X 8

(DLL)

SCLK may not be a uniform clock depending upon value of devnum, mode, and MNP.

M = 1 - 128

N = 1 - 16

P = 1 - 8

When:

P1 = 8, DLL(PLL) is Enabled

devnum = Number of Channels in Cascade.

Note That for a Standalone Device, devnum = 2.

Mode = 1 (For Continious Data Transfer Mode)

Mode = 2 (For Programming Mode)

TLV320AIC20, TLV320AIC21

TLV320AIC24, TLV320AIC25

TLV320AIC20K, TLV320AIC24K

SLAS363D – MARCH 2002 – REVISED APRIL 2005

The sampling frequency is the frequency of the frame sync (FS) signal where falling edge starts digital-data

transfer for both ADC and DAC. The sampling frequency is derived from the master clock (MCLK) input by the

following equations:

•

Coarse sampling frequency (default):

– The coarse sampling is selected by programming P = 8 in the control register 4, which is the default

configuration of AIC2x on power-up or reset.

– FS = Sampling (conversion) frequency = MCLK / (16 x M x N x 8)

•

Fine sampling frequency (see Note 5):

– FS = Sampling (conversion) frequency = MCLK/ (16 x M x N x P)

NOTE:

1. Use control register 4 to set the following values of M, N, and P

2. M = 1, 2, . . . , 128

3. N = 1, 2, . . . , 16

4. P = 1, 2, . . . , 8

5. The fine sampling rate needs an on-chip phase lock loop (frequency multiplier) to

generate internal clocks. The output of the PLL is only used to generate internal

clocks that are needed by the data converters. Other clocks such as the serial

interface clocks in master mode are not generated from the PLL output. The clock

generation scheme is as shown in Figure 18. The PLL requires the relationship

between MCLK and P to meet the following condition: 10 MHz

≤ (MCLK/P) ≤ 25

MHz.

Figure 18. Clock Timing

6. Selecting the Fine sampling mode turns on the analog PLL, which starts

generating after a finite time delay. The internal clocks are required to be present

in order to enable the DAC output drivers. Therefore, turning on any output drivers

immediately after turning on the PLL causes the output of the DAC to go to the

common-mode voltage. While using the PLL, the output drivers must first be

enabled before the PLL is enabled in order to ensure correct operation of the part.

This implies that register 6B for channel 1 and channel 2 in the codec must be

programmed before register 4.

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