TLV320AIC21 datasheet(33/56 Pages) TI1

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Control Register Programming

Data Frame Format

D15 - D1

A/D and D/A Data

D15 - D0

A/D and D/A Data

D15 - D0

DIN

(15+1) Bit Mode

(Continuous Data Transfer Mode Only)

DOUT

(16 Bit A/D Data)

DIN

16 Bit Mode

DOUT

16 Bit Mode

Control Frame

Request

Control Frame Format (Programming Mode)

Broadcast Register Write

TLV320AIC20, TLV320AIC21

TLV320AIC24, TLV320AIC25

TLV320AIC20K, TLV320AIC24K

SLAS363D – MARCH 2002 – REVISED APRIL 2005

Each channel in the TLV320AIC2x contains six control registers that are used to program available modes of

operation. All register programming occurs during the control frame through DIN. New configuration takes effect

after a delay of one frame sync. The TLV320AIC2x is defaulted to the programming mode upon power up. Set bit

6 in control register 1 to switch to continuous data transfer mode. If the 15+1 data format of DIN has been

selected, the LSB of the DIN to 1 to switch from continuous data transfer mode to programming set mode.

Otherwise, either the device needs to be reset or the host port writes 0 to bit D6 of each codec's control register

1 during the continuous data transfer mode to switch back to the programming mode. The control registers are

replicated for each channel in the AIC2x, and these need to be programmed separately for the individual

channels. Register bits that control resources that are common to both channels are shadowed (i.e., writing to

the appropriate register bit of one channel is automatically reflected in the register bits for the other channel).

See the control register tables for a more detailed description of the exact register bits that are shadowed.

Figure 28. Data Frame Format

During the control frame, the DSP sends 16-bit words to each codec's time slot SMARTDM(TM) through DIN to

read or write control registers in each codec shown in Table 4. The upper byte (Bits D15-D8) of the 16-bit

control-frame word defines the read/write command. Bits D15-D13 define the control register address with

write command is used to perform the broadcast mode. During a register write, the register content is located in

the lower byte of DIN. During a register read, the register content is output in the lower byte of DOUT in the

same control frame, whereas the lower byte of DIN is ignored.

Broadcast operation is very useful for a cascading system of SMARTDM codecs in which all register

programming can be completed in one control frame. During the control frame and in any register-write time slot,

if the broadcast bit (D11) is set to 1, the register content of that time slot is written into the specified register of all

devices in cascade (see Figure 29). This reduces the DSP's overhead of doing multiple writes to program the

same data into cascaded devices.

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