TLV320AIC21 datasheet(24/56 Pages) TI1

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IIR/FIR Control

Overflow Flags

IIR/FIR Bypass Mode

System Reset and Power Management

Software and Hardware Reset

TLV320AIC20, TLV320AIC21

TLV320AIC24, TLV320AIC25

TLV320AIC20K, TLV320AIC24K

SLAS363D – MARCH 2002 – REVISED APRIL 2005

Functional Description (continued)

The decimation IIR/FIR filter sets an overflow flag (bit D7) of control register 1 indicating that the input analog

signal has exceeded the range of internal decimation filter calculations. The interpolation IIR/FIR filter sets an

overflow flag (bit D4) of control register 1 indicating that the digital input has exceeded the range of internal

interpolation filter calculations. When the IIR/FIR overflow flag is set in the register, it remains set until the user

reads the register. Reading this value resets the overflow flag. These flags need to be reset after power up by

reading the register. If FIR/IIR overflow occurs, the input signal should be attenuated by either the PGA or some

other method.

An option is provided to bypass IIR/FIR filter sections of the decimation filter and the interpolation filter. This

mode is selected through bit D6 of control register 2 and effectively increases the frequency of the FS signal to

four times normal output rate of the IIR/FIR-filter. For example, for a normal sampling rate of 8 Ksps (i.e., FS = 8

kHz) with IIR/FIR, if the IIR/FIR is bypassed, the frequency of FS is readjusted to 4×8 kHz = 32 kHz. The sync

filters of the two paths can not be bypassed. A maximum of four devices in cascade can be supported in the

IIR/FIR bypass mode.

In this mode , the ADC channel outputs data which has been decimated only till 4 FS. Similarly DAC channel

input needs to be preinterpolated to 4 FS before being given to the device. This mode allows users the flexibility

to implement their own filter in DSP for decimation and interpolation. M should be a multiple of 4 during IIR/FIR

bypass mode.

The TLV320AIC2x resets internal counters and registers in response to either of two events:

•

A low-going reset pulse is applied to terminal RESET

•

A 1 is written to the programmable software reset bits (D3 of control register 3A)

NOTE: The TLV320AIC2x requires a power-up reset applied to the RESET pin.

Either event resets the control registers and clears all sequential circuits in the device. The H/W RESET (active

low) signal is at least 6 master clock periods long. As soon as the RESET input is applied, the TLV320AIC2x

enters the initialization cycle that lasts for 132 MCLKs, during which the serial port of the DSP must be 3-stated.

The initialization sequence performed by the AIC2x is known as Auto Cascade Detection (ACD). ACD is a

mechanism that allows a device to know its address in a cascade chain. Up to 8 AIC2x devices can be cascaded

together.

The Master device is the first device on the chain i.e. the FS of the Master is connected to the FS of the DSP.

During ACD, each device gets to know the number of devices in the chain as well as its relative position in the

chain. This is done upon hardware reset. Therefore. after power up, a hardware reset must be completed. ACD

requires 132 MCLKs after reset to complete operation. The number of MCLKs is independent of the number of

devices in the chain.

Adjacent devices in the chain have their FS and FSD pins connected to each other. The master device’s FS is

connected to the FS pin of the DSP. The FSD pin on the last device in the chain is pulled high for master-slave

configuration, and it is pulled low for stand-alone slave configuration.

The master device has the highest address i.e., the master device has address equal to total no of channels in

cascade minus 1. For example, if 8 devices are cascaded, then the master device has address 15 and 14

followed by the next device which has 13 and 12 etc.

During the first 64 MCLKs, FS is configured as an output and FSD as an input.

During the next 64 MCLKs, FS is configured as an input and FSD as an output.

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