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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TLV320AIC21 датащи(PDF) 27 Page - Texas Instruments |
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TLV320AIC21 датащи(HTML) 27 Page - Texas Instruments |
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27 / 56 page  www.ti.com DIN/DOUT (16 Bit) MSB LSB D15 D14 D15 D14 0 1 30 31 29 D1 FS 32 SCLKs D1 D0 MSB LSB D0 Master (CH 1) Slave (CH 2) SCLK (Output) Cascade Mode and Frame-Sync Delayed (FSD) TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K SLAS363D – MARCH 2002 – REVISED APRIL 2005 Figure 19. Timing Diagram for FS in the Continuous Transfer Mode In cascade mode, the DSP should be in slave mode, i.e., it receives all frame-sync pulses from the master though the master's FS. The master's FSD is output to the first slave and the first slave's FSD is output to the second slave device and so on. Figure 20 shows the cascade of four TLV320AIC2xs in which the closest one to DSP is the master and the rest are slaves. The FSD output of each device is input to the FS terminal of the succeeding device. Figure 21 shows the FSD timing sequence in the cascade. 27 |
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