TLV320AIC21 datasheet(13/56 Pages) TI1

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Analog

Loopback

PGA

Low Pass

Filter

Sigma-

Delta

DAC

Anti-

Aliasing

Filter

Sigma-

Delta

ADC

Sinc

Filter

FIR Filter

IIR Filter

Decimation Filter

Sinc

Filter

FIR Filter

IIR Filter

Interpolation Filter

Digital Loopback

w/ Sidetone Control

and Mute

M/S

DOUT

DIN

SCLK

FSD

PGA

SMARTDM

-9 dB to -27 dB

Serial

Port

0 dB to 42 dB (1.5 dB Steps)

48 dB, 54 dB

Vref

CODEC

0 dB to -42 dB (1.5 dB Steps)

-48 dB, -54 dB

TLV320AIC20, TLV320AIC21

TLV320AIC24, TLV320AIC25

TLV320AIC20K, TLV320AIC24K

SLAS363D – MARCH 2002 – REVISED APRIL 2005

Functional Block Diagram (One of Two Channels Shown)

Definitions and Terminology

Data Transfer

The time during which data is transferred from DOUT and to DIN.

Interval

The interval is 16 shift clocks, and the data transfer is initiated by

the falling edge of the FS signal.

Signal Data

This refers to the input signal and all of the converted representations

through the ADC channel and the signal through the DAC channel to the

analog output. This is contrasted with the purely digital software control

data.

Frame Sync

Frame sync refers only to the falling edge of the signal FS that initiates

the data transfer interval

Frame Sync and Sampling Period

Frame sync and sampling period is the time between falling edges of

successive FS signals.

The sampling frequency

ADC Channel

ADC channel refers to all signal processing circuits between the analog

input and the digital conversion result at DOUT.

DAC channel

DAC channel refers to all signal processing circuits between the digital

data word applied to DIN and the differential output analog signal

available at OUTP and OUTM.

Dxx

Bit position in the primary data word (xx is the bit number)

DSxx

Bit position in the secondary data word (xx is the bit number)

The alpha character d represents valid programmed or default data in the

control register format (see Section 3.2, Secondary Serial Communi-

cation) when discussing other data bit portions of the register.

PGA

Programmable gain amplifier

IIR

Infinite impulse response

FIR

Finite impulse response

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