STA400A datasheet(25/117 Pages) STMICROELECTRONICS

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STA400A

stable in the high state. A START condition must precede any command for data transfer.

Stop Condition

STOP is identified by low to high transition of the data bus SDA signal while the clock signal SCL is stable

in the high state. A STOP condition terminates communications between STA400A and the bus master.

Acknowledge Bit

An acknowledge bit is used to indicate a successful data transfer. The bus transmitter, either master or

slave, will release the SDA bus after sending 8 bits of data.

During the 9th clock pulse the receiver pulls the SDA bus low to acknowledge the receipt of 8 bits of data.

Some registers do not give acknowledge when the data is not available.

Data Input

During the data input the STA400A samples the SDA signal on the rising edge of the clock SCL. For cor-

rect device operation the SDA signal has to be stable during the rising edge of the clock and the data can

change only when the SCL line is low.

Device Addressing

To start communication between the master and the STA400A, the master must initiate with a start con-

dition. Following this, the master sends onto the SDA line 8 bits (MSB first) corresponding to the device

select address and read or write mode.

The 7 most significant bits are the device address identifier, corresponding to the I2C bus definition. For

the STA400A these are fixed as 1101010.

The 8th bit (LSB) is the read or write operation bit (RW; set to 1 in read mode and to 0 in write mode).

After a START condition the STA400A identifies on the bus the device address and, if matched, it will

acknowledges the identification on SDA bus during the 9th bit time.

The following 2 bytes after the device identification byte are the internal space address.

Write Operation (see fig. 15)

Following a START condition the master sends a device select code with the RW bit set to 0.

The STA400A gives the acknowledge and waits for the 2 bytes of internal address. The least significant

15 bits of the 2 bytes address provides access to any of the internal registers. The most significant bit

means incremental mode (1 = auto incremental enabled, 0 = auto incremental disabled).

The STA400A has an internal byte address counter. Each time a byte is written or read, this counter, ac-

cording to the autoincremental bit setting, is incremented or not.

After the reception of each of the internal bytes address the STA400A again responds with an acknowl-

edge.

Byte Write

In the byte write mode the master sends one data byte and this is acknowledged by STA400A. The mas-

ter then terminates the transfer by generating a STOP condition. The Multibyte Write needs the auto in-

cremental mode bit set to '1'.

Multibyte Write

The multibyte write mode can start from any internal address. The master sends the data and each one

is acknowledged by the STA400A. The transfer is terminated by the master generating a STOP condition.

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