STA400A datasheet(24/117 Pages) STMICROELECTRONICS

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STA400A

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PCTS_EF, Payload Channel TSCC Sync / Reed-Solomon Error Flag

The PCDC frequency can be set from 11.96 MHz to 373.75 kHz via the 5 MSBs of the PCDC_CONF register

(PCDC_CONF[6:2]); the clock polarity and the clock configuration (always running or fixed to '1' when the inter-

face is not transmitting data) can be configured via the PCDC_CONF[1] and the PCDC_CONF[0] bits respec-

tively.

The PCSD data format can be set via the PCSD_CONF register; PCSD_CONF[0] and PCSD_CONF[1] define

if data are transmitted MSB or LSB first and if a parity bit is appended or not to each data byte respectively

The calculated parity can be even or odd depending on the content of PCSD_CONF[2] bit.

PCFS is the PRC packet synchronization; the default setting is one pulse at the beginning of each burst of 448

bytes. PCBS is a byte synchronization signal with one pulse at the beginning of each decoded data byte (de-

fault configuration).

PCTS_EF can be configured as the TSCC synchronization signal (default configuration) or as the Reed-So-

lomon error flag signal. The TSCC synchronization is a pulsed signal having period T=432ms (one pulse every

TDM frame).

The width of the synchronization pulses is equal to 1 PCDC cycle. The parameters of these last three signals

can be configured via the PCSYNC_CONF register.

1.7 MICROPOCESSOR INTERFACE

Data communication between the microcontroller and the device takes place through the 2 wires (SDA and

SCL) IIC-bus interface. The STA400A is always a slave device.

The STA400A Register Map is organized in 8 main pages with a base address given in Table 2.2. After the de-

vice address, to read or write a register, the microcontroller must send first the base-address to select one of

the 8 pages and a relative-address to select the register inside the page. The STA400A has byte or multibytes

registers access with different classes (see table 2.1); the complete list of the registers is given in the Register

Map section.

Interrupt Line

The interrupt line of the STA400A (pin 53 - INTR) OR-Wires 8 different interrupt requests from the CDEC that

can be individually masked by the registers IRQ1_MASK (address 0x0417).

The interrupt vector is represented by the IRQ1_STATUS register (address 0x0419) described in section 2.6.

After an interrupt request, the INTR pin remains at high level, except for the MFP_CLK interrupt bit5, that is an

impulse periodic signal. The IRQ1_STATUS interrupt vector may be automatically reset after the read operation

or may be reset by the microcontroller (writing 0x00) depending on the bit0 of the CONTROL register (see sec-

tion 2.6)

IIC-BUS Specification

The I2C-bus protocol defines any device that sends data on to the bus as a transmitter and any device that reads

the data as a receiver. The device that controls the data transfer is known as the master and the others as the

slave. The master will always initiate the transfer and will provide the serial clock for synchronisation.

Data Transition or Change

Data changes on the SDA line must only occur when the SCL clock is low. SDA transitions while the clock

is high are used to identify START or STOP condition.

Start Condition

START is identified by a high to low transition of the data bus SDA signal while the clock signal SCL is

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