STA400A datasheet(23/117 Pages) STMICROELECTRONICS

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STA400A

The depunctured R=1/3 coded data stream (equal for combined-satellite and terrestrial) is decoded by the Vit-

erbi Decoder using 6 bit of quantization (1 hard bit and 5 soft bits). The outer decoding process, the block

deinterleaving and the satellite/terrestrial selective combining is performed by the RS decoder circuit. Additional

feature of the FEC block is the Bit Error Rate estimation (computed separately for terrestrial and combined sat-

ellite) based on the re-encoding of the Viterbi decoded bit-stream.

1.6 PC BITSTREAM INTERFACES

After demodulation, TDM processing and FEC decoding the CDEC delivers the TSCC and the selected PRCs

to external devices for further processing. To implement this function, STA400A contains two identical Payload

Channel (PC) Bitstream Interfaces (see fig.1).

Each PC Interface performs the parallel to serial conversion and the reformatting of the data packets coming

from the PRC Demux Control block and provides serial data, clock and synchronization signals to the PC output

ports.

The Payload Channel output protocol (showed in fig.14) is configurable, independently for the two interfaces,

via the PC interface registers described in section 2.7.

Figure 14. PC Bitstream Output Protocol

The 432ms TDM frame is divided in 50 time intervals with the first two containing the TSCC data. Each time

interval contains a burst of 448 bytes (2 header bytes H1 and H2, and 446 bytes of PRC data) transmitted from

the PRC Demux to the PC Interface.

The PC output ports are enabled depending on the settings of the register Pcid Data Wr (addr: 0x0651-0x0652).

Each output port provides 5 signals:

PCSD, Payload Channel Serial Data

PCDC, Payload Channel Data Clock

PCFS, Payload Channel PRC Frame Sync

PCBS, Payload Channel Byte Sync

PCSD

PCDC

PCFS

432ms frame period

CLOCK

TSCC1

TSCC2

PRC_An

PRC_A1

PRC_B1

PRC_Zn

PRC_Z1

PRC_Bn

PCSD

PCDC

PCFS

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