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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STA400A датащи(PDF) 94 Page - STMicroelectronics |
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STA400A датащи(HTML) 94 Page - STMicroelectronics |
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94 / 117 page  STA400A 94/117 bols before starting the BER computation. b2: IQ SWAP Swap between I and Q components of the received symbols b1-b0: PHCHG Phase ambiguity correction 00 = 0 degrees 01 = 90 degrees 10 = 180 degrees 11 = 270 degrees CONTROL - General Purpose Control Register This register controls the master clock outputs, the bidirectional buses mode to access the external memory and the BIST access mode (reserved for structural test). b7: MCLKO_OFF MCLKO output buffer disable. 0 = Buffer active; 1 = Buffer disabled (output fixed to ground). b6: MCLKON_OFF MCLKON output buffer disable. 0 = Buffer active; 1 = Buffer disabled (output fixed to ground). b5: MDQM_CTRL External memory input/output mask polarity. 0 = High level active; 1 = Low level active. b4-b1: Reserved b0: IRQ_RST_CTRLReset after read on the interrupt register (IRQ1_STATUS) 0 = Disabled; 1 = Enabled. IRQ1_MASK - Interrupt Mask Register Enable/Disable interrupts on INTR pin. Type: SingleByte - R/W Word Length: 3 Byte Name Address (Hex) Bit Map Reset Value (Hex) QPSK_BER_CTRL 040D 2-0 00 Type: SingleByte - R/W Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex) CONTROL 0410 7-0 00 Type: SingleByte - R/W Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex) IRQ1_MASK 0417 7-0 00 |
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