 |
поискавой системы для электроныых деталей |
|
|
поискавой системы для электроныых деталей |
|
DP8430V датащи(PDF) 1 Page - National Semiconductor (TI) |
|
|
|
|||||||||||||||||||||||||||||
DP8430V датащи(HTML) 1 Page - National Semiconductor (TI) |
|
|
1 / 56 page  TLF11118 July 1993 DP8430V31V32V-33 microCMOS Programmable 256k1M4M Dynamic RAM ControllerDrivers General Description The DP8430V31V32V dynamic RAM controllers provide a low cost single chip interface between dynamic RAM and all 8- 16- and 32-bit systems The DP8430V31V32V gen- erate all the required access control signal timing for DRAMs An on-chip refresh request clock is used to auto- matically refresh the DRAM array Refreshes and accesses are arbitrated on chip If necessary a WAIT or DTACK out- put inserts wait states into system access cycles including burst mode accesses RAS low time during refreshes and RAS precharge time after refreshes and back to back ac- cesses are guaranteed through the insertion of wait states Separate on-chip precharge counters for each RAS output can be used for memory interleaving to avoid delayed back to back accesses because of precharge An additional fea- ture of the DP8432V is two access ports to simplify dual accessing Arbitration among these ports and refresh is done on chip Features Y On chip high precision delay line to guarantee critical DRAM access timing parameters Y microCMOS process for low power Y High capacitance drivers for RAS CAS WE and DRAM address on chip Y On chip support for nibble page and static column DRAMs Y Byte enable signals on chip allow byte writing in a word size up to 32 bits with no external logic Y Can use a single clock source Up to 33 MHz operating frequency Y On board Port APort B (DP8432V only)refresh arbitra- tion logic Y Direct interface to all major microprocessors Y 4 RAS and 4 CAS drivers (the RAS and CAS configura- tion is programmable) of Pins of Address Largest Direct Drive Access Control (PLCC) Outputs DRAM Memory Ports Possible Capacity Available DP8430V 68 9 256 kbit 4 Mbytes Single Access Port DP8431V 68 10 1 Mbit 16 Mbytes Single Access Port DP8432V 84 11 4 Mbit 64 Mbytes Dual Access Ports (A and B) Block Diagram DP8430V31V32V DRAM Controller TLF11118 – 1 FIGURE 1 TRI-STATE is a registered trademark of National Semiconductor Corporation Staggered RefreshTM is a trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation RRD-B30M75Printed in U S A |
Аналогичный номер детали - DP8430V |
|
Аналогичное описание - DP8430V |
|
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Russian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
